Gerald Lynn Leake2436 Greenock Buena Vista Rd, Mckeesport, PA 15135

Gerald Leake Phones & Addresses

2436 Greenock Buena Vista Rd, McKeesport, PA 15135 (412) 751-0393 (412) 751-2556 (412) 751-5581

Englewood, FL

2436 Greenock Buena Vista Rd, McKeesport, PA 15135 (267) 987-3035

Work

Position: Sales Occupations

Education

Degree: Associate degree or higher

Emails

Mentions for Gerald Lynn Leake

Gerald Leake resumes & CV records

Resumes

Gerald Leake Photo 10

32Nm Development Integration Engineering

Location:
Mckeesport, PA
Industry:
Semiconductors
Work:
IBM since Jan 2009
32nm Development Integration Engineering
IBM May 2006 - Jan 2009
Manufacturing Integration Engineering
IBM Jan 2001 - May 2006
Integration Engineering - SRDC
Atmel corporation Aug 1999 - Dec 2000
Photolithography Engineer
Education:
Penn State University 1994 - 1999
B.S., Material Science and Engineering
Skills:
Integration Engineering, Development, Unix, Integration
Gerald Leake Photo 11

Owner

Location:
Mckeesport, PA
Industry:
Machinery
Work:

Owner

Publications & IP owners

Us Patents

Methods Of Forming Cmos Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques

US Patent:
2008012, May 29, 2008
Filed:
Nov 27, 2006
Appl. No.:
11/563476
Inventors:
Min Chul Sun - Gyeonggi-do, KR
Jong Ho Yang - Fishkill NY, US
Young Gun Ko - Fishkill NY, US
Ja Hum Ku - Gyeonggi-do, KR
Jae Eon Park - Gyeonggi-do, KR
Jeong Hwan Yang - Gyeonggi-do, KR
Christopher Vincent Baiocco - Newburgh NY, US
Gerald Leake - McKeesport PA, US
International Classification:
H01L 21/8238
H01L 21/336
US Classification:
438230, 438303, 257E21409, 257E21632
Abstract:
Methods of forming field effect transistors include methods of forming PMOS and NMOS transistors by forming first and second gate electrodes on a substrate and then forming an electrically insulating layer having etch-enhancing impurities therein, on the first and second gate electrodes. The electrically insulating layer may be formed as a boron-doped silicon nitride layer or an electrically insulating layer that is doped with germanium and/or fluorine. The electrically insulating layer is etched-back to define first sidewall spacers on the first gate electrode and second sidewall spacers on the second gate electrode. P-type source and drain region dopants are then implanted into the semiconductor substrate, using the first sidewall spacers as a first implant mask. The second sidewall spacers on the second gate electrode are then etched back to reduce their lateral dimensions. N-type source and drain region dopants are then implanted into the semiconductor substrate, using the second sidewall spacers with reduced lateral dimensions as a second implant mask.

NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.