Gordon T Carskadon, Age 522913 Perceval Ln, Austin, TX 78748

6904436, Jun 7, 2005

Oct 4, 2000

09/684160

James Daniel Merchant - Starkville MS, US
Gordon Carskadon - Starkville MS, US
Brian P. Evans - Starkville MS, US
Jeffery Scott Hunt - Ackerman MS, US
Anup Nayak - Fremont CA, US
Andrew Wright - Mountain View CA, US

Cypress Semiconductor Corporation - San Jose CA

G06F007/08

707100, 707101

A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.

6490712, Dec 3, 2002

Oct 4, 2000

09/684159

James Daniel Merchant - Starkville MS
Gordon Carskadon - Starkville MS
Brian P. Evans - Starkville MS
Jeffery Scott Hunt - Ackerman MS
Anup Nayak - Fremont CA
Andrew Wright - Mountain View CA

Cypress Semiconductor Corporation - San Jose CA

G06F 1750

716 12, 716 17, 716 18

A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e. g. , a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.

2020040, Dec 24, 2020

Jun 21, 2019

16/449285

- Santa Clara CA, US
Dinesh Somasekhar - Portland OR, US
Clifford Ong - Portland OR, US
Eric A Karl - Portland OR, US
Zheng Guo - Hillsboro OR, US
Gordon Carskadon - Austin TX, US

G11C 11/56
H01L 27/112
G11C 17/12

Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.