People Background Check
Find People:

Hao Lin Chen, Age 84904 Kelley Ct, Lafayette, CA 94549

Get Report
Known as:
Hao Lin Te Chen Hao L Chen Haolin Ying Chen Haolin L Chen Haolin W Chen Ying Chen Haolin Hanlin Chen Hadlin Chen Haolin Cjen Lin Chen Hao Chen Hao-Lin Chen Hanlin
Related to:
Weldon Bob Chen 52

Hao Chen Phones & Addresses

904 Kelley Ct, Lafayette, CA 94549 (925) 938-4327

El Cerrito, CA

1750 16Th St NW APT 14, Washington, DC 20009 (202) 986-6816

Walnut Creek, CA

Dublin, CA

Albany, CA

Danville, CA

San Ramon, CA

Show more

Mentions for Hao Lin Chen

Career records & work history

Lawyers & Attorneys

Hao Chen Photo 1

Hao Chen - Lawyer

Address:
Clifford Chance LLP
(212) 320-7226 (Office)
Licenses:
New York - Due to reregister within 30 days of birthday 2009
Education:
Harvard Law School
Nanjing University Law School

Medicine Doctors

Hao Chen Photo 2

Hao Chen, San Francisco CA

Specialties:
Acupuncture
Address:
835 Clay St Suite 103, San Francisco, CA 94108
(415) 834-9893 (Phone)
Languages:
English

License Records

Hao Chen

Licenses:
License #: 0402049436
Category: Professional Engineer License

Hao Chen

Licenses:
License #: 0225089621
Category: Real Estate Individual

Hao Chen

Phone:
(347) 348-7482
Licenses:
License #: 80377 - Active
Category: Health Care
Issued Date: Nov 10, 2015
Effective Date: Nov 10, 2015
Expiration Date: Aug 31, 2017
Type: Massage Therapist

Hao Chen resumes & CV records

Resumes

Hao Chen Photo 48

Hao Chen - Hyattsville, MD

Work:
APICS student 2014 to 2014 Faw-Volkswagen Automobile Co.Ltd - Changchun, CN 2013 to 2013
Assistant Designer Faw-Toyota Motor Co.Ltd 2012 to 2012
Assistant Production Coordinator Bay Laurel Catering - Seattle, WA 2010 to 2012
Food Products Coordinator
Education:
University of Washington - Seattle, WA 2014
Bachelor of Art Robert H. Smith School of Business, University of Maryland - College Park, MD
Master of Science in Supply Chain Management
Hao Chen Photo 49

Hao Chen - Pleasanton, CA

Work:
Advanced Ion Beam Technology Inc Jun 2013 to 2000
Sr. Electrical Engineer/Project Leader Hospira Inc - San Jose, CA Oct 2012 to Jun 2013
Design Electrical Engineer Cymer Inc - San Diego, CA Jun 2010 to Oct 2012
Senior Electronics Engineer University of Southern California - Los Angeles, CA Aug 2004 to May 2010
Research Assistant
Education:
University of Southern California - Los Angeles, CA 2004 to 2010
Ph.D in Electrical Engineering University of Science and Technology of China - Hefei, CN 1999 to 2003
Bachelor's in Physics
Hao Chen Photo 50

Hao Chen - Frederick, MD

Work:
First Home Care Foundation May 2006 to Present
System Administrator Points of Light Foundation - Washington, DC Jan 2004 to May 2006
IT Support Gestalt Technology - Hickory, NC Aug 2002 to Jan 2004
Programmer Kuehne & Nagel Inc 1998 to 2000
Customer Service Representative
Education:
Southeastern University - Washington, DC 2000 to 2002
M.S. in Computer Science Nanjing University 1994 to 1998
B.A. in Chinese Literature
Hao Chen Photo 51

Hao Chen - San Francisco, CA

Work:
BTRAX, INC Nov 2012 to 2000
Marketing & Administration Assistant CHINESE INFORMATION AND NETWORKING ASSOCIATION Oct 2012 to 2000
Public Relations TIGER LADIES LLC Feb 2012 to 2000
Financing & Marketing Director GOLDSTATE SECURITIES COMPANY - Guangzhou, China Mar 2011 to May 2011
Marketing Assistant in Marketing Department GOLDSTATE SECURITIES COMPANY - Guangzhou, China Feb 2011 to Mar 2011
Financial Assistant in Operating Department CHINA EVERBRIGHT BANK - Guangzhou, China Nov 2009 to Dec 2009
Customer Service
Education:
SCHOOL OF MANAGEMENT, UNIVERSITY OF SAN FRANCISCO - San Francisco, CA 2012
Master of Science in Financial Analysis SOUTH CHINA AGRICULTURE UNIVERSITY - Guangzhou, China 2006 to 2010
Bachelor in Finance
Skills:
Skilled in quantitative and qualitative analysis, team building, details summary, professional software (including E-views), social media connection and public relations

Publications & IP owners

Us Patents

Memory Controller With Loopback Test Interface

US Patent:
7836372, Nov 16, 2010
Filed:
Jun 8, 2007
Appl. No.:
11/760566
Inventors:
Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G01R 31/28
G11C 29/00
US Classification:
714743, 714718
Abstract:
In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Combined Single Error Correction/Device Kill Detection Code

US Patent:
8055975, Nov 8, 2011
Filed:
Jun 5, 2007
Appl. No.:
11/758322
Inventors:
Brian P. Lilly - San Francisco CA, US
Robert Gries - Woodstock CT, US
Sridhar P. Subramanian - Cupertino CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03M 13/00
US Classification:
714758, 714784, 714785
Abstract:
In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

Memory Controller With Loopback Test Interface

US Patent:
8086915, Dec 27, 2011
Filed:
Oct 21, 2010
Appl. No.:
12/909073
Inventors:
Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G01R 31/28
G11C 29/00
G06F 11/00
US Classification:
714716, 714719, 714743
Abstract:
In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Combined Single Error Correction/Device Kill Detection Code

US Patent:
8219880, Jul 10, 2012
Filed:
Sep 27, 2011
Appl. No.:
13/246736
Inventors:
Brian P. Lilly - San Francisco CA, US
Robert Gries - Woodstock CT, US
Sridhar P. Subramanian - Cupertino CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03M 13/00
US Classification:
714758, 714784, 714785
Abstract:
In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

Memory Controller With Loopback Test Interface

US Patent:
8301941, Oct 30, 2012
Filed:
Nov 28, 2011
Appl. No.:
13/305202
Inventors:
Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G01R 31/28
G11C 29/00
G06F 11/00
US Classification:
714716, 714718, 714743
Abstract:
An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Memory Controller With Qos-Aware Scheduling

US Patent:
8314807, Nov 20, 2012
Filed:
Sep 16, 2010
Appl. No.:
12/883864
Inventors:
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G09G 5/39
US Classification:
345531
Abstract:
In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Frequency Doubling Using A Photo-Resist Template Mask

US Patent:
8357618, Jan 22, 2013
Filed:
Oct 24, 2008
Appl. No.:
12/257953
Inventors:
Christopher Dennis Bencher - San Jose CA, US
Huixiong Dai - San Jose CA, US
Li Yan Miao - San Francisco CA, US
Hao Chen - Santa Clara CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/31
US Classification:
438763, 438689, 438703, 257313, 257E2124
Abstract:
A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.

Hybrid Element Enabling Solid/Sph Coupling Effect

US Patent:
8374833, Feb 12, 2013
Filed:
Jun 14, 2010
Appl. No.:
12/815112
Inventors:
Hao Chen - Pleasanton CA, US
Jingxiao Xu - Dublin CA, US
Chi-Hsien Wang - Pleasanton CA, US
Assignee:
Livermore Software Technology Corporation - Livermore CA
International Classification:
G06G 7/48
US Classification:
703 6
Abstract:
Hybrid elements that enable coupling effects between SPH particles and FEM solid are disclosed. According to one aspect of the present invention, hybrid elements are configured to facilitate coupling effect of solid element based on finite element method (FEM) and one or more corresponding particles based on smoothed particle hydrodynamics (SPH). Hybrid elements are defined in a computer aided engineering (CAE) grid model as a buffer or interface between the SPH particles and FEM solids. For example, a portion of the grid model comprises SPH particles because the likelihood of enduring large deformation, while the rest of the model comprises FEM solid elements. Hybrid elements are placed between the solids and the particles. Each hybrid element comprises two layers: solid layer and particle layer.

Isbn (Books And Publications)

Network And Parallel Computing: Ifip International Conference, Npc 2004, Wuhan, China, October 18-20, 2004. Proceedings

Author:
Hao Chen
ISBN #:
3540233881

Possible Relatives

De X Chen  Deanna M Chen  Daisy C Chen  Deborah L Chen  Danny W Chen  Dennis C Chen  Denny C Chen  Hao Lam  Hao A Ngo  Hao D Truong 

NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.