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Harry I Linzer, Age 688117 Olde Hill Ct, Raleigh, NC 27615

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Known as:
Harry A Linzer
Related to:
Kathryn L Linzer 98 Milton Linzer

Harry Linzer Phones & Addresses

8117 Olde Hill Ct, Raleigh, NC 27615 (919) 847-3697

Trent Woods, NC

Poughkeepsie, NY

Saugerties, NY

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Mentions for Harry I Linzer

Harry Linzer resumes & CV records

Resumes

Harry Linzer Photo 12

Principal Engineer

Location:
Durham, NC
Industry:
Semiconductors
Work:
Marvell Semiconductor
Principal Engineer Globalfoundries
Senior Technical Staff Member Ibm Jun 1978 - Jun 2015
Senior Technical Staff Member, Asics and System on A Chip
Education:
Syracuse University 1978 - 1985
Master of Science, Masters, Computer Engineering New York University - Polytechnic School of Engineering 1974 - 1978
Bachelors, Bachelor of Science, Electrical Engineering, Computer Engineering
Skills:
Asic, Soc, Static Timing Analysis, Computer Architecture, Processors, Logic Design, Debugging, Vlsi, Functional Verification, Tcl, Dft, Verilog, Eda, Ic, Microprocessors, Semiconductors, Embedded Systems, Hardware Architecture, Vhdl, Perl, Physical Design, Rtl Design, Timing Closure, Cmos, Circuit Design, Fpga, Simulations, Hardware, Integrated Circuit Design, System Architecture, High Performance Computing, Firmware, Device Drivers, Shell Scripting, Powerpc, Software Engineering, Embedded Software, Algorithms, Systemverilog, C, C++, Analog Circuit Design, Modelsim, Unix, Arm, Embedded Linux, Pcie, Technical Leadership, Formal Verification, Mixed Signal
Harry Linzer Photo 13

Senior Technical Staff Member At Ibm Corporation

Position:
Senior Technical Staff Member, ASICs and System on a Chip at IBM Corporation
Location:
Raleigh-Durham, North Carolina Area
Industry:
Semiconductors
Work:
IBM Corporation since Jun 1978
Senior Technical Staff Member, ASICs and System on a Chip
Education:
Syracuse University 1978 - 1985
MS Computer Engineering, Computer Engineering Polytechnic University 1974 - 1978
BS Electrical Engineering, Computer Engineering
Skills:
ASIC, TCL, EDA, Processors, Logic Design, Verilog, VLSI, Computer Architecture, SoC, Hardware Architecture, Microprocessors, Functional Verification, Static Timing Analysis, SystemVerilog, Semiconductors, Physical Design, Debugging, RTL design, VHDL, Embedded Systems, Perl, Circuit Design, Timing Closure, CMOS, IC, High Performance Computing, ModelSim, FPGA, Firmware, Simulations, Hardware, Integrated Circuit Design, C, C++, Device Drivers, Shell Scripting, System Architecture, PowerPC, Unix, Software Engineering, ARM, Embedded Software, Algorithms, Analog Circuit Design, Embedded Linux, DFT, PCIe

Publications & IP owners

Us Patents

System And Method For Detecting Cable Faults For High-Speed Transmission Link

US Patent:
7378853, May 27, 2008
Filed:
Feb 27, 2004
Appl. No.:
10/708384
Inventors:
Louis L. Hsu - Fishkill NY, US
Harry I. Linzer - Raleigh NC, US
James Rockrohr - Hopewell Junction NY, US
Huihao H. Xu - Brooklyn NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/02
US Classification:
324543
Abstract:
A system and method of detecting a fault in a transmission link are provided which includes providing a selectable reference level according to one of a direct current (DC) mode threshold and an alternating current (AC) mode threshold, wherein the DC mode threshold is a fixed potential and the AC mode threshold varies with time. An input signal arriving from the transmission link is compared to one of the DC mode threshold and the AC mode threshold to determine whether a fault is present in the transmission link.

Methods For The Support Of Jtag For Source Synchronous Interfaces

US Patent:
7685484, Mar 23, 2010
Filed:
Nov 14, 2007
Appl. No.:
11/939751
Inventors:
Harry I. Linzer - Raleigh NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714724
Abstract:
Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver.

Managing Redundant Memory In A Voltage Island

US Patent:
7710800, May 4, 2010
Filed:
Dec 12, 2007
Appl. No.:
11/954479
Inventors:
Harry I Linzer - Raleigh NC, US
Michael R. Ouellette - Westford VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
365200, 365201, 36518909, 36518905
Abstract:
An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions.

Development Tool For Comparing Netlists

US Patent:
8255846, Aug 28, 2012
Filed:
Aug 18, 2009
Appl. No.:
12/543301
Inventors:
William Alan Binder - Morrisville NC, US
Harry I. Linzer - Raleigh NC, US
William Appleton Rose - Wake Forest NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716104, 716101, 716126, 716139
Abstract:
System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is generated for one of the netlists and a normalized score is generated for the other netlist. The baseline reference score and the normalized score are used to generate a similarity score that is displayed on a display monitor. Preferably, the similarity score is displayed as a percentage.

Methods For The Support Of Jtag For Source Synchronous Interfaces

US Patent:
2009012, May 14, 2009
Filed:
Aug 11, 2008
Appl. No.:
12/189304
Inventors:
Harry I. Linzer - Raleigh NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/3177
G06F 11/25
US Classification:
714727, 714E11155
Abstract:
Exemplary embodiments of the present invention comprise a method for the support of a JTAG interface for the testing of connectivity between integrated circuits. The method comprises delivering output from a JTAG register to a primary register, delivering a JTAG control signal to the primary register and a clock signal gating control logic, delivering output from the primary register and a secondary register to a multiplexer, delivering clock signal output from the clock signal gating control logic to the multiplexer, wherein the clock signal is delivered is a constant and known value, and delivering the output from the multiplexer to an I/O driver.

Memory Subsystem Having A Static Row Memory And A Dynamic Ram

US Patent:
5421000, May 30, 1995
Filed:
Jul 26, 1993
Appl. No.:
8/097931
Inventors:
Ronald N. Fortino - Raleigh NC
Harry I. Linzer - Raleigh NC
Kim E. O'Donnell - Raleigh NC
Assignee:
International Business Machines Corp. - Armonk NY
International Classification:
G06F 1200
US Classification:
395425
Abstract:
A computer memory subsystem is comprised of one or more Dynamic Random Access Memory (DRAM) arrays with on-chip sense latches for storing data outputted from the DRAM, an on-chip Static Random Access Memory (SRAM) functioning as a Distributed Cache and an on-chip multiplexor. A first data bus interconnects the sense latches, the SRAM and the multiplexor. A second data bus interconnects the multiplexor and the SRAM. A memory controller generates signals which cause information to be extracted from the DRAM while the contents of the SRAM is unchanged or vice versa.

Method And Apparatus For Controlling Operation Of A Cache Memory During An Interrupt

US Patent:
5371872, Dec 6, 1994
Filed:
Oct 28, 1991
Appl. No.:
7/783551
Inventors:
Larry D. Larsen - Raleigh NC
David W. Nuechterlein - Durham NC
Kim E. O'Donnell - Raleigh NC
Lee S. Rogers - Raleigh NC
Thomas A. Sartorius - Raleigh NC
Kenneth D. Schultz - Cary NC
Harry I. Linzer - Raleigh NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1208
US Classification:
395425
Abstract:
The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.

System And Method For Program Execution Tracing Within An Integrated Processor

US Patent:
5809293, Sep 15, 1998
Filed:
Jul 29, 1994
Appl. No.:
8/283128
Inventors:
Jeffrey Todd Bridges - Raleigh NC
Thomas K. Collopy - Cary NC
James N. Dieffenderfer - Apex NC
Thomas Joseph Irene - Raleigh NC
Harry I. Linzer - Raleigh NC
Thomas Andrew Sartorius - Raleigh NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 900
US Classification:
395568
Abstract:
A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.

Possible Relatives

David Linzer  Harry L Johnson  Harry A Standley  Harry D Johnston  Harry E Jolly  Harry N Stanton  Harry P Whitehead  Harry W Staub  Harry S Whitehouse  Harry H Whiteley 

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