Henry N KwongBerkeley, CA

Henry Kwong Phones & Addresses

Berkeley, CA

Work

Company: Williams-sonoma, inc May 2007 Position: Systems engineer

Mentions for Henry N Kwong

Career records & work history

Medicine Doctors

Henry M. Kwong

Specialties:
Ophthalmology
Work:
Henry M Kwong MD
607 Rue De Brille, New Iberia, LA 70563
(337) 367-1247 (phone) (337) 365-7496 (fax)
Education:
Medical School
Tulane University School of Medicine
Graduated: 1974
Procedures:
Lens and Cataract Procedures
Conditions:
Cataract, Glaucoma, Keratitis, Macular Degeneration, Primary Angle-Closure Glaucoma, Retinal Detachments
Languages:
English
Description:
Dr. Kwong graduated from the Tulane University School of Medicine in 1974. He works in New Iberia, LA and specializes in Ophthalmology. Dr. Kwong is affiliated with Iberia Medical Center.
Henry Kwong Photo 1

Henry Mark Kwong

Specialties:
Ophthalmology
Education:
Tulane University (1974)

Henry Kwong resumes & CV records

Resumes

Henry Kwong Photo 37

Owner At Kai Wingerter & Partner

Position:
owner at Kai Wingerter & Partner
Location:
San Francisco Bay Area
Industry:
Internet
Work:
Kai Wingerter & Partner
owner
Henry Kwong Photo 38

Henry Kwong

Henry Kwong Photo 39

Henry Kwong - Elk Grove, CA

Work:
Williams-Sonoma, Inc May 2007 to 2000
Systems Engineer
International Business Machines - Rocklin, CA Mar 2006 to May 2007
Systems Analyst
GAP, Inc - San Francisco, CA Oct 2005 to Mar 2006
Systems Analyst
Data Systems Search Consultants - Walnut Creek, CA Aug 2004 to Dec 2004
Lead Systems Engineer
TekSystems, Inc - Sacramento, CA Mar 2003 to Jun 2003 GAP, Inc Oct 2002 to Jan 2003
Lead Systems Engineer
NaviSite, Inc Jul 1998 to Dec 2001
UNIX Systems Engineer
NaviSite, Inc - San Jose, CA Jul 1997 to Dec 2001 NaviSite, Inc Jul 1997 to Jul 1998
Supervisor
Borland Intl Mar 1995 to Jul 1997
Supervisor
Borland Intl - Scotts Valley, CA Sep 1989 to Jul 1997 Borland Intl Sep 1989 to Mar 1995
Computer Operator
Shipping Clerk Dec 1987 to Sep 1989

Publications & IP owners

Us Patents

Memory Mapped Register File And Method For Accessing The Same

US Patent:
7558942, Jul 7, 2009
Filed:
Jan 25, 2006
Appl. No.:
11/339049
Inventors:
Hong-Yi Chen - Fremont CA, US
Henry Hin Kwong Fan - San Mateo CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 9/34
US Classification:
711220, 711202, 712 43, 712208, 712229
Abstract:
A data processing system comprises a processor to process instructions. A plurality of pipeline stages to execute instructions including a register file. The register file includes a memory unit having a plurality of memory locations, each memory location being addressable by an encoded address. The encoded address corresponds to at least one register and processing mode. Input ports receive inputs for addressing at least one of the memory locations using an encoded address. Output ports to output data from at least one of the memory locations using an encoded address.

Memory Mapped Register File And Method For Accessing The Same

US Patent:
7568083, Jul 28, 2009
Filed:
Sep 17, 2003
Appl. No.:
10/666892
Inventors:
Hong-Yi Chen - Fremont CA, US
Henry Hin Kwong Fan - San Mateo CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 9/34
US Classification:
711220, 711202, 712 43, 712208, 712229
Abstract:
A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by an encoded address, wherein the encoded address corresponds to at least one register and processor mode. The input ports receive inputs for addressing at least one memory location using an encoded address. The output ports output data from at least memory location addressable by an encoded address.

Memory Mapped Register File

US Patent:
7882332, Feb 1, 2011
Filed:
Oct 13, 2008
Appl. No.:
12/287782
Inventors:
Hong-Yi Hubert Chen - Fremont CA, US
Henry Hin Kwong Fan - San Mateo CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 9/34
US Classification:
711220, 711202, 712208, 712218, 712229
Abstract:
A register system for a data processing system includes an address encoder that generates an encoded address based on a processor mode identifier and a register identifier and memory comprising 2unbanked registers. The encoded address identifies one of the 2unbanked registers associated with one of the P processor modes. The encoded address comprises T bits. The register identifier identifies one of 2unbanked registers. The processor mode identifier identifies P processor modes, where T and P are integers greater than two.

Memory Mapped Register File

US Patent:
8078828, Dec 13, 2011
Filed:
Jan 31, 2011
Appl. No.:
13/017867
Inventors:
Hong-Yi Chen - Fremont CA, US
Henry Hin Kwong Fan - San Mateo CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 9/34
US Classification:
711220, 711202, 712208, 712218, 712229
Abstract:
A method and apparatus for operating a memory mapped register file. The method includes: receiving a source index input having a length of T−1 bits, the source index input identifying one of a plurality of unbanked registers; receiving a processor mode input to identify one of P processor modes, where P is greater than two; generating an encoded address having a length of T bits based on the source index input and the processor mode input; and identifying one of the plurality of unbanked registers associated with one of the P processor modes using the encoded address.

Memory Mapped Register File

US Patent:
7437532, Oct 14, 2008
Filed:
Jul 25, 2003
Appl. No.:
10/627269
Inventors:
Hong-Yi Chen - Fremont CA, US
Henry Hin Kwong Fan - San Mateo CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 12/10
US Classification:
711220, 711202, 712 43, 712208, 712229
Abstract:
A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by an encoded address, wherein the encoded address corresponds to a respective one of the plurality of registers and a corresponding processor mode. The input ports receive inputs for addressing at least one register using an encoded address. The output ports output data from at least register addressable by an encoded address.

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