Son Thai Ho, Age 454728 N Laporte Ave, Chicago, IL 60630

7216276, May 8, 2007

Feb 27, 2003

10/375986

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US

Marvell International Ltd. - Hamilton

G01R 31/28

714733, 714724, 714 30, 714 45

An integrated circuit which utilizes a serial trace output interface instead of the known parallel trace output interface for transferring test data from the integrated circuit, thereby reducing the number of pins needed for outputting test data. Specifically, a preferred embodiment of the present invention uses a serializer/deserializer (SERDES) interface which captures output testing data in frames, serializes the framed data, and outputs the serialized data on at least one pin. The output serialized data is deserialized, and the deserialized data is synchronized in order to find the frame boundaries. The synchronized frames are then unpacked to retrieve the original testing data. Another preferred embodiment of the present invention uses a bi-directional SERDES both for inputting testing and debugging instructions and data from the analysis software and for outputting testing and debugging results and data to the analysis software.

7250751, Jul 31, 2007

Oct 5, 2005

11/243697

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US

Marvell International Ltd. - Hamilton

G01R 31/28

3241581

A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.

7250784, Jul 31, 2007

Jul 26, 2005

11/189458

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US

Marvell International Ltd. - Hamilton

G01R 31/02
G01R 31/28
G11C 7/00
G01C 29/00

324763, 365201, 714733, 714734, 714718

A hard disk drive system includes an external interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. The hard disk drive system includes a system on chip (SOC) that includes a controller and a read/write channel that communicates with the controller and that includes an integrated system test (IST) module that communicates with the external interface. A memory module communicates with the SOC and includes memory and an IST module. The hard disk drive system includes a spindle/voice coil motor driver module that includes an IST module. At least one of the IST modules is a master IST module that receives the test configuration data and that configures the IST modules for testing at least one of the controller, the read/write channel, and the memory module.

7253652, Aug 7, 2007

Oct 5, 2005

11/243661

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US

Marvell International Ltd. - Hamilton

G01R 31/02

324763

A system on chip (SOC), comprises an external interface that receives test configuration data, transmits test result data, and that transmits and receives application data. A plurality of SOC components, each including an integrated system test (IST) module, wherein at least one of the SOC components includes a controller that communicates with the external interface. At least one of the plurality of SOC components communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing the plurality of SOC components.

7439729, Oct 21, 2008

Oct 5, 2005

11/243660

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US

Marvell International Ltd. - Hamilton

G01R 31/28
G11B 27/36
G11B 20/00
G06F 11/00

3241581, 360 31, 369 531, 714738

A hard disk drive system comprises N hard disk drive means for performing hard disk drive functions and is connected in a daisy chain, wherein N is greater than one. The system includes integrated system test (IST) means for testing and that is integrated with a first one of the N hard disk drive means and includes pattern generating means for generating test pattern data and pattern monitoring means for receiving a returned test pattern. The pattern generating means generates test pattern data that is routed from the first one of the N hard disk drive means serially through the remaining ones of the N hard disk drive means and back to the first one of the N hard disk drive means. The pattern monitoring means generates test result data based on returned test data returned to the first one of the N hard disk drive means.

7444571, Oct 28, 2008

Feb 24, 2005

11/065584

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US
Daniel Smathers - Boulder CO, US

Marvell International Ltd. - Hamilton

G01R 31/28

714733, 714724, 714734, 714 30, 714 45, 703 28

A system for testing a target integrated circuit comprises a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the integrated circuit and that analyzes received data from the target integrated circuit. A first interface module communicates with the host device and formats the test instructions and data using a first format. A first serializer serializes the test instructions and data. A first deserializer on the target integrated circuit communicates with the first serializer and deserializes the test instructions and data. A control module on the target integrated circuit communicates with the first deserializer, interprets the test instructions and data using the first format. A testing module receives the interpreted test instructions and data from the control module and performs testing and debugging of the target integrated circuit.

7496812, Feb 24, 2009

May 17, 2005

11/131073

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US
Daniel Smathers - Boulder CO, US

Marvell International Ltd. - Hamilton

G01R 31/28
G06F 11/00
G06F 9/455
G06F 13/00

714724, 714 25, 714 30, 714 31, 714 39, 714732, 714733, 714734, 710317

An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer that serializes at least one of first control data and/or test data from at least one of the first and/or second interface modules. A second path from the integrated circuit to the first and second interface modules and the analyzer includes a high speed deserializer that deserializes serial data containing at least one of test result data and/or second control data from the integrated circuit. A frame sync module synchronizes data from the high speed deserializer to identify frames. The high speed deserializer outputs the second control data to at least one of the first and/or second interface modules. The frame sync module outputs the frames to the analyzer.

7496818, Feb 24, 2009

Jul 11, 2005

11/178807

Saeed Azimi - Union City CA, US
Son Ho - Los Altos CA, US
Daniel Smathers - Boulder CO, US

Marvell International Ltd. - Hamilton

G01R 31/28

714733, 714 30, 714 45, 714724, 714734, 714741, 703 28, 341100, 375224, 370366

A system is provided that retrieves test information from a target integrated circuit. A serializer receives the test information in a first format and divides and reformats the test information into first and second serial messages. The serializer is located on the target integrated circuit and has a first serial output that sends the first serial message and a second serial output that sends the second serial message. A deserializer communicates with the first and second serial outputs and receives the first and second serial messages. The deserializer retrieves a first portion of the test information from the first serial message, a second portion of the test information from the second serial message, and reconstructs the test information from the first portion and the second portion.