Jin LeeWestminster, CO

6509622, Jan 21, 2003

Aug 23, 2000

09/644639

Qing Ma - San Jose CA
Jin Lee - Palo Alto CA
Quan Tran - San Jose CA
Harry Fujimoto - Sunnyvale CA

Intel Corporation - Santa Clara CA

H01L 27095

257483, 438132, 438215, 438601

An integrated circuit including a die having a circuit area and a plurality of guard rings. The circuit area includes active devices, passive devices, and interconnects connected to form an integrated circuit. The plurality of guard rings includes a plurality of stacked guard rings having substantially equal widths and encircling the circuit area. Alternatively, the plurality of guard rings includes metallization level guard rings interleaved with one or more via level guard rings. Each of the one or more via level guard rings includes one or more guard rings encircling the circuit area. Alternatively, the plurality of guard rings includes a plurality of concentric guard rings encircling the circuit area. Each of the plurality of guard rings is fabricated from a metal, such as aluminum, copper, or silver, or an alloy of aluminum, copper, or silver.

6537706, Mar 25, 2003

Mar 14, 2000

09/525198

Qing Ma - San Jose CA
Jin Lee - Palo Alto CA
Jun Fei Zheng - Mountain View CA
Giang Dao - Fremont CA

Intel Corporation - Santa Clara CA

G03F 900

430 5, 430323, 430296, 430394, 378 35

A method for making a photolithographic mask. The method comprises forming a film on a substrate that deforms the substrate, and applying a deformation reducing agent to the substrate to reduce the amount of deformation that the film caused. In a preferred embodiment, the deformation reducing agent comprises one or more films, which are formed on one side of the substrate, that balance the substrate deformation effect of one or more films that are deposited on the other side of the substrate. The film or films that constitute the deformation reducing agent may be similar to, or different from, an absorption film and/or any other films deposited on the substrate or on the absorption film.

6737754, May 18, 2004

Feb 5, 2001

09/777833

Qing Ma - San Jose CA
Jin Lee - Palo Alto CA
Chun Mu - Saratoga CA
Quat Vu - Santa Clara CA
Jian Li - Sunnyvale CA
Larry Mosley - Sunnyvale CA

Intel Corporation - Santa Clara CA

H01L 2328

257796, 257707, 257712, 257713

A semiconductor device having a multilayer laminate that includes a thermally stable, flexible polymer film, a semiconductor die, a molding compound, and a heat dissipation member. The die has an active surface and an inactive surface, in which the active surface includes a plurality of contacts. The molding compound contacts both the laminate and the die, but does not contact the dies active or inactive surfaces. The heat dissipation member contacts the dies inactive surface.

6806708, Oct 19, 2004

Jun 17, 2003

10/464296

Jin Hyung Lee - Menlo Park CA
John M. Pauly - Redwood City CA
Dwight G. Nishimura - Palo Alto CA

The Board of Trustees of the Leland Standford Junior University - Palo Alto CA

G01V 300

324307, 324309

Imaging time using PILS is reduced by using multiple coils with localized sensitivities with each coil having a separate demodulation channel thereby permitting parallel signal processing and image reconstruction. Images from the multiple coils are then combined to form an image with a larger field of view (FOV).

6876053, Apr 5, 2005

Aug 13, 1999

09/374502

Qing Ma - San Jose CA, US
Jin Lee - Mountain View CA, US
Harry Fujimoto - Sunnyvale CA, US
Changhong Dai - San Jose CA, US
Travis Eiles - San Jose CA, US
Krishna Seshan - San Jose CA, US

Intel Corporation - Santa Clara CA

H01L029/00
H01L029/76
H01L031/113
H01L031/119

257500, 257369, 257374, 257499, 257401, 257506

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i. e. , to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

7277597, Oct 2, 2007

Jun 17, 2003

10/464236

Jin Hyung Lee - Menlo Park CA, US
John M. Pauly - Redwood City CA, US
Dwight G. Nishimura - Palo Alto CA, US

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

G06K 9/36

382280

A modified projection on convex sets (POCS) algorithm and method for partial k-space reconstruction using low resolution phase maps for scaling full sets of reconstructed k-space data. The algorithm can be used with partial k-space trajectories in which the trajectories share a common point such as the origin of k-space, including variable-density spiral trajectories, projection reconstruction trajectories with a semicircle region acquisition, and projection reconstruction trajectories with every other spike acquired.

7330602, Feb 12, 2008

Sep 17, 2004

10/944381

Jin Hung Lee - Menlo Park CA, US
Brad Osgood - Stanford CA, US
Dwight G. Nishimura - Palo Alto CA, US

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

G06K 9/64

382278, 382276, 382284

An optimal sampling pattern for variable density sampling of a continuous signal uses a statistical knowledge of the signal to determine an autocorrelation matrix from which a basis set is identified. Sampling is performed at locations determined from an eigenvector matrix, and the sampled output provides coefficients for the basis set. The reconstructed signal output is a summation of the multiplication of the coefficients and the basis set.

7410858, Aug 12, 2008

May 19, 2006

11/437379

Qing Ma - San Jose CA, US
Jin Lee - Mountain View CA, US
Harry Fujimoto - Sunnyvale CA, US
Changhong Dai - San Jose CA, US
Travis Eiles - San Jose CA, US
Krishna Seshan - San Jose CA, US

Intel Corporation - Santa Clara CA

H01L 29/72

438221, 438197, 438404, 438424, 438694

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i. e. , to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.