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Ian Livingston13820 S 44Th St UNIT 1345, Phoenix, AZ 85044

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Known as:
Joeanne Walls
Related to:
Maggie E Gleeson 57 Margaret E Ulmer 72 Lillian Livingston 76 Latasha Nicole Ulmer 44 Kenny D Ulmer 36

Ian Livingston Phones & Addresses

13820 44Th St, Phoenix, AZ 85044

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Ian Livingston resumes & CV records

Resumes

Ian Livingston Photo 40

Principal Design Engineer

Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Renesas Electronics Corporation
Principal Design Engineer Microchip Technology
Senior Process Integration Engineer Ii Freescale Semiconductor Aug 1998 - Apr 2004
Senior Device Engineer Allegro Microsystems, Llc Oct 1994 - Apr 1996
Photo and Etch Process Engineer Harris Semiconductor Inc 1990 - 1993
Co-Op
Education:
Arizona State University 2013 - 2018
Doctorates, Doctor of Philosophy, Electrical Engineering, Electronics, Electronics Engineering, Philosophy Rochester Institute of Technology 1996 - 1998
Master of Science, Masters, Engineering Rochester Institute of Technology 1987 - 1993
Bachelors, Bachelor of Science, Engineering Williamsport Area High School 1983 - 1987
Skills:
Silicon, Semiconductors, Cmos, Jmp, Design of Experiments, Process Integration, Ic, Failure Analysis, Microelectronics, Spc, Analog, Yield, Product Engineering, Silvaco, Semiconductor Device, Integrated Circuits, Statistical Process Control, Mixed Signal, Thin Films, Cadence Virtuoso, Cadence Icfb, Cadence Spectre, Mosfet, Electronics, Semiconductor Industry, Process Engineering, Manufacturing, Cross Functional Team Leadership, Matlab
Ian Livingston Photo 41

Ian Livingston

Ian Livingston Photo 42

Ian Livingston

Ian Livingston Photo 43

Ian Livingston

Ian Livingston Photo 44

Ian Livingston

Publications & IP owners

Wikipedia

Ian Livingston Photo 53

Ian Livingst

Ian Livingston (born 28 July 1964, in Glasgow, Scotland is the Chief Executive Officer of BT Group (commonly known as British Telecom). The fourth generation son

Us Patents

Multiple Well Drain Engineering For Hv Mos Devices

US Patent:
2013002, Jan 31, 2013
Filed:
Jul 20, 2012
Appl. No.:
13/554890
Inventors:
Gregory Dix - Tempe AZ, US
Leighton E. McKeen - Gilbert AZ, US
Ian Livingston - Chandler AZ, US
Roger Melcher - Gilbert AZ, US
Rohan Braithwaite - Gilbert AZ, US
International Classification:
H01L 21/336
H01L 29/78
US Classification:
257288, 438286, 257E29255, 257E21409
Abstract:
At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.

Isbn (Books And Publications)

El Talisman De La Muerte/The Talisman Of Death

Author:
Ian Livingston
ISBN #:
8437221080

Possible Relatives

Dale A Livingston  Debbie C Livingston  Dallas M Livingston  Dan Livingston  Dee A Livingston  Denise D Livingston  Dennis L Livingston  Ian S Johnston  Ian Jolly  Ian D Jones 

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