Iraj Emami706 Walnut St, Calvin, TX 78602

6452412, Sep 17, 2002

Mar 4, 1999

09/262238

Richard W. Jarvis - Austin TX
Iraj Emami - Austin TX
Charles E. May - Gresham OR

Advanced Micro Devices, Inc. - Sunnyvale CA

G01R 3126

324765, 438 17

A drop-in test structure fabricated upon a production integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology are described. The test structure may be fabricated upon an integrated circuit elevational profile formed according to a subset of steps within a sequence of steps of the integrated circuit production methodology that culminates in a production integrated circuit intended for use by a consumer. According to an embodiment, the integrated circuit elevational profile may be fabricated according to a majority of the sequence of steps. Alternatively, the integrated circuit elevational profile may be fabricated according to a minority of the sequence of steps. The test structure may be fabricated upon die sites designated to receive the test structure. Alternatively, the test structure may be fabricated upon die sites otherwise intended for operable integrated circuits.

6560504, May 6, 2003

Sep 29, 1999

09/408241

Thomas J. Goodwin - Austin TX
Iraj Emami - Austin TX
Charles E. May - Gresham OR

Advanced Micro Devices, Inc. - Austin TX

G06F 1900

700121, 438 14

A method is provided for manufacturing, the method including processing a workpiece in a processing step, detecting defect data after the processing of the workpiece in the processing step has begun and forming an output signal corresponding to at least one type of defect based on the defect data. The method also includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step to reduce the at least one type of defect.

7158896, Jan 2, 2007

Nov 1, 2004

10/978604

Bhanwar Singh - Morgan Hill CA, US
Khoi A. Phan - San Jose CA, US
Ramkumar Subramanian - Sunnyvale CA, US
Bharath Rangarajan - Sunnyvale CA, US
Iraj Emami - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 19/00

702 31, 700120, 700121, 438 5, 438 7, 438 14, 438 16

Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.

7221060, May 22, 2007

Mar 8, 2005

11/074602

Bhanwar Singh - Morgan Hill CA, US
Khoi A. Phan - San Jose CA, US
Bharath Rangarajan - Sunnyvale CA, US
Iraj Emami - Austin TX, US
Ramkumar Subramanian - Sunnyvale CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 23/544

257797, 438462, 365150

Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

7334202, Feb 19, 2008

Jun 3, 2005

11/145327

Bhanwar Singh - Morgan Hill CA, US
Qiaolin Zhang - Albany CA, US
Iraj Emami - Austin TX, US
Joyce S. Oey Hewett - Austin TX, US
Luigi Capodiece - Santa Cruz CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 17/50

716 4

A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.

7373215, May 13, 2008

Aug 31, 2006

11/469206

Jason Phillip Cain - Sunnyvale CA, US
Bhanwar Singh - Morgan Hill CA, US
Iraj Emami - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 19/00

700121, 700 29

The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e. g. , a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e. g. , to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.

7460922, Dec 2, 2008

Dec 7, 2005

11/298340

Bhanwar Singh - Morgan Hill CA, US
Jason Phillip Cain - Sunnyvale CA, US
Harish Kumar Bolla - Sunnyvale CA, US
Iraj Emami - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 19/00

700121, 700 98, 438 40

The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is a mapping component that converts the transistor performance into exposure dose values and a process tool that communicates the exposure dose value to a scanner. The exposure dose value is fed back for optimization of future chip exposures. The disclosed embodiments directly optimize transistor performance, thus controlling an important parameter in many integrated circuits.

6242273, Jun 5, 2001

Sep 29, 1999

9/408232

Thomas J. Goodwin - Austin TX
Iraj Emami - Austin TX
Charles E. May - Gresham OR

Advanced Micro Devices, Inc. - Austin TX

H01L 2166
G01R 3126

438 14

A method is provided for manufacturing, the method including processing a workpiece in a processing step and detecting defect data after the processing of the workpiece in the processing step has begun. The method also includes filtering the defect data using a fractal filter and forming an output signal corresponding to at least one type of defect based on the fractally filtered defect data. The method further includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step to reduce the at least one type of defect.