Jack T Lavier, Age 4820932 NE 44Th St, Sammamish, WA 98074

7449912, Nov 11, 2008

Jan 26, 2007

11/627730

Kelly Jean Pracht - Fort Collins CO, US
Samuel M. Babb - Fort Collins CO, US
Jack Lavier - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G01R 31/36

324771, 324118, 324521

Power supplies are disclosed herein. One embodiment of a power supply comprises a first input and a second input, wherein the first input and the second input are connectable to a pulse width modulation controller and wherein a pulse width modulation signal is outputable from the pulse width modulation controller. A power stage connected to the first input and the second input. A first comparator having a first comparator first input is connected to the first input and a first comparator second input connected to the output of the power stage. A change of voltage at the output of the first comparator constitutes a difference in phase between the first input and the output of the power stage.

2002012, Sep 12, 2002

Mar 7, 2001

09/800851

John Hutton - Fort Collins CO, US
William Hudson - Fort Collins CO, US
Daniel Halperin - Fort Collins CO, US
Daniel Krueger - Fort Collins CO, US
Jack Lavier - Fort Collins CO, US
Mark Musgrove - Fort Collins CO, US

G06F001/04
G06F001/06
G06F001/08

713/500000

The present invention bundles four ring oscillators, a 20-bit ripple counter and the necessary control logic needed to implement a JTAG scan based interface. The present system can be located on every die, so that each location can be individually tested. It communicates with the outside world through a standard JTAG interface. It is accessible at wafer, package, and system test which allows for several methods of correlating the oscillator speed to the speed of a part in the actual system.

2008009, Apr 24, 2008

Oct 24, 2006

11/585545

Kelly Jean Pracht - Fort Collins CO, US
Jack Lavier - Fort Collins CO, US
Samuel M. Babb - Fort Collins CO, US

H02B 1/24

307116

Systems and methods for providing redundant voltage regulation are provided. A representative method incorporates: providing a first voltage regulator and a second voltage regulator, the second voltage regulator having output rectifiers; electrically connecting the first voltage regulator to a load such that the first voltage regulator independently powers the load; disabling the output rectifiers of the second voltage regulator; detecting a fault of the first voltage regulator; responsive to the fault, enabling the output rectifiers of the second voltage regulator such that the second voltage regulator independently powers the load.

2013032, Dec 5, 2013

Apr 28, 2011

13/985757

Peter Mardilovich - Corvallis OR, US
Jack Lavier - Corvallis OR, US

B41J 2/045

347 14

In an embodiment, a method of compensating for capacitance change in a piezoelectric element of a fluid ejection device includes sensing a current driving a piezoelectric element, determining from the current that capacitance of the piezoelectric element has changed, and altering a rise time of the current driving the piezoelectric element to compensate for the changed capacitance.

2020037, Nov 26, 2020

Mar 3, 2020

16/808286

- Redmond WA, US
Andrew PUTNAM - Redmond WA, US
Daniel FIRESTONE - Redmond WA, US
Jack LAVIER - Redmond WA, US

G06F 9/455
G06F 13/42
G06F 11/07

A physical server with an offload card including a SoC (system-on-chip) and a FPGA (field programmable gate array) is disclosed. According to one set of embodiments, the SoC can be configured to offload one or more hypervisor functions from a CPU complex of the server that are suited for execution in software, and the FPGA can be configured to offload one or more hypervisor functions from the CPU complex that are suited for execution in hardware.

2019035, Nov 21, 2019

May 17, 2018

15/983041

- Redmond WA, US
Jack Thomas LAVIER - Sammamish WA, US
Robert Glenn RUNDELL - Bellevue WA, US

Microsoft Technology Licensing, LLC - Redmond WA

H03B 5/04
H03B 5/36
H03H 7/06

Examples are disclosed that relate to oscillator circuits. One example provides a circuit comprising an amplifier, a resonator in parallel with the amplifier, and a shunt path including one or more circuit elements, the shunt path coupled to a first node downstream of an output of the amplifier and to a second node, the shunt path configured to shunt current received at the first node away from an input of the resonator and toward the second node, the second node having, at steady state, a relatively lower voltage than an input voltage of the resonator.

2008023, Oct 2, 2008

Mar 29, 2007

11/729646

Jack Lavier - Ft. Collins CO, US
Samuel M. Babb - Ft. Collins CO, US
Kelly Jean Pracht - Ft. Collins CO, US

H02H 7/00
G01R 31/02

361 18, 324537

A control logic detects voltage regulator failure in a power supply. The control logic comprises first and second lines configured for respective connection to a controller node and a phase node of a voltage regulator, a delay element coupled to the first line configured to delay signals at the controller node into alignment with signals at the phase node, and a level detector coupled to the second line configured to convert the signals at the phase node into at least two digital representations indicative of respective signal thresholds. A logic compares timing of the delayed signals with the digital representations and detects occurrence of a voltage regulator fault based on the timing comparison.