James F Asbrock, Age 741402 Pambara Cir, Oceanside, CA 92054

James Asbrock Phones & Addresses

1402 Pambara Cir, Oceanside, CA 92054 (760) 439-3154 (760) 439-4195

2909 Via Carrio, Carlsbad, CA 92008

Hillsboro, OR

1402 Pambara Cir, Oceanside, CA 92054 (209) 838-7496

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James F Asbrock

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Work

Company: Nu-trek and aerius/flir Sep 2011 Position: Ic design

Education

Degree: Master of Science, Masters School / High School: University of Cincinnati 1978 to 1978 Specialities: Engineering

Skills

Sensors • Asic • Testing • Simulations

Emails

Industries

Design

Mentions for James F Asbrock

James Asbrock resumes & CV records

Resumes

James Asbrock Photo 11

Ic Design

Location:
Oceanside, CA
Industry:
Design
Work:
Nu-Trek and Aerius/Flir
Ic Design
Raytheon 1978 - Sep 2011
Engineering Fellow
Raytheon Jan 1999 - Jan 2011
Senior Design Engineer
Raytheon Jan 1994 - Jan 1999
Senior Project and Design Engineer
Hughes Aircraft Company Jan 1978 - Jan 1994
Project Engineer and Line Manager
Purcell High School Xavier University Jan 1972 - Jan 1976
Teacher
Education:
University of Cincinnati 1978 - 1978
Master of Science, Masters, Engineering
Xavier University 1972 - 1972
Bachelors, Bachelor of Science, Physics
Skills:
Sensors, Asic, Testing, Simulations

Publications & IP owners

Us Patents

Low Noise, Low Power And High Bandwidth Capacitive Feedback Trans-Impedance Amplifier With Differential Fet Input And Bipolar Emitter Follower Feedback

US Patent:
7626460, Dec 1, 2009
Filed:
Oct 30, 2007
Appl. No.:
11/980294
Inventors:
Kanon Liu - Arcadia CA, US
James F. Asbrock - Oceanside CA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H03F 3/16
US Classification:
330300
Abstract:
A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads.

High Resoultion Digital Imaging Apparatus

US Patent:
8120683, Feb 21, 2012
Filed:
Apr 6, 2000
Appl. No.:
09/544561
Inventors:
Tumay O Tumer - Riverside CA, US
Shi Yin - Riverside CA, US
Dale G. Maeding - Dana Point CA, US
James Asbrock - Oceanside CA, US
Martin Yaffe - Toronto, CA
Gordon Mawdsley - Toronto, CA
James Mainprize - North York, CA
Assignee:
Nova R & D, Inc. - Riverside CA
International Classification:
H04N 3/14
H01L 27/146
US Classification:
348295, 25037009
Abstract:
An integrated application specific integrated circuit having a detection layer, a time delayed integration capability, data acquisition electronics, and a readout function is provided for detecting breast cancer in women. The detection layer receives x-ray radiation and converts the received energy to electron pairs, one of which is received by pixels. The time delay integration is on the chip and a part of the readout architecture. The detector may be a hybrid silicon detector (SiPD), a CdZnTe detector, or a GaAs detector.

Read Out Integrated Circuit

US Patent:
8373458, Feb 12, 2013
Filed:
Nov 17, 2009
Appl. No.:
12/619870
Inventors:
Kanon Liu - Arcadia CA, US
Bryan W. Kean - Fairfax VA, US
James F. Asbrock - Oceanside CA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H03L 7/00
US Classification:
327143
Abstract:
According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.

System And Method For Ranging Of Targets

US Patent:
8477291, Jul 2, 2013
Filed:
Dec 16, 2009
Appl. No.:
12/639417
Inventors:
John E. Clement - Santa Barbara CA, US
James F. Asbrock - Oceanside CA, US
William O. McKeag - Santa Barbara CA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
G01C 3/08
US Classification:
356 501, 356 504
Abstract:
A method for ranging or targets may include transmitting a pulse of electromagnetic energy at a target. The method may also include generating a time-varying signal in response to receiving a first signal indicating transmission of the pulse of electromagnetic energy. Additionally, the method may include detecting a reflection of the pulse from the target. Moreover, the method may include generating a second signal indicating detection of the reflection. The method may further include generating a third signal substantially equivalent to the second signal delayed by predetermined delay. The method may also include sampling the time-varying signal in response to receiving the third signal.

Imaging System

US Patent:
2002014, Oct 3, 2002
Filed:
Mar 29, 2001
Appl. No.:
09/821320
Inventors:
Truc Vu - Tustin CA, US
Frank Calabretta - Costa Mesa CA, US
James Asbrock - Oceanside CA, US
Nhan Do - San Jose CA, US
International Classification:
H04N005/335
US Classification:
257/294000, 348/294000
Abstract:
A detector with a transistor sensitive to electromagnetic energy. In accordance with the present teachings, the transistor is biased such that the output thereof is responsive to the electromagnetic energy. The inventive imager includes an array of the novel detectors. Each of the detectors being an n-channel metal-oxide semiconductor transistor with a floating body. The transistors are biased for selective activation and sequential readout. The transistor outputs are read by a differential current sense amplifier. A color filter is disclosed to provide a color sense capability. As an alternative, a grating is provided for this purpose. The present invention allows a very dense imager to be built on using conventional silicon on sapphire or silicon on insulator complementary metal-oxide semiconductor processes. The use of standard CMOS processes allows for low manufacturing costs.

Readout Integrated Circuit (Roic) For Laser Detection And Ranging (Ladar) System And Method For Using Same

US Patent:
2006023, Oct 19, 2006
Filed:
Apr 18, 2005
Appl. No.:
11/108921
Inventors:
James Asbrock - Oceanside CA, US
George Dietrich - Murphy TX, US
Lloyd Linder - Agoura Hills CA, US
International Classification:
G01C 3/08
G06K 9/00
US Classification:
356004030, 356004010, 382106000
Abstract:
Disclosed is a LADAR system and a method for operating same. The LADAR system includes circuitry for generating the electrical signal with an optical signal detector using N discrete samples; a bank of M parallel sample/hold circuit unit cells individual ones of which operate with an associated sample/hold clock, where each sample/hold clock is shifted in time by a fixed or programmable amount Δt relative to a sample/hold clock of an adjacent sample/hold circuit unit cell; and further includes circuitry for sequentially coupling a sampled value of the electrical signal from a first output of individual ones of at least some of the M parallel sample/hold circuit unit cells to an analog to digital converter circuit. Each of the M parallel sample/hold circuit unit cells has a second output for outputting a digital signal for indicating the state (low or high) during a time that the associated sample/hold clock allowing for time of arrival determination. The LADAR system further includes or is coupled to a signal processor for deriving an image of the object and a range to the object based on signals at the first and second outputs. Assuming an effective sample/hold circuit sampling rate of X samples per second, a sampling rate of each of the M parallel sample/hold circuit unit cells can be X/M samples per second.

Method And Apparatus For Integrated Sensor To Provide Higher Resolution, Lower Frame Rate And Lower Resolution, Higher Frame Rate Imagery Simultaneously

US Patent:
2013008, Apr 11, 2013
Filed:
Oct 11, 2011
Appl. No.:
13/270557
Inventors:
Richard H. Wyles - Santa Barbara CA, US
James F. Asbrock - Oceanside CA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H04N 7/18
H04N 5/335
US Classification:
348144, 348294, 348148, 348E07085, 348E05091
Abstract:
Methods and apparatus to provide, from data from a single sensor, high-resolution imagery at a first frame rate, such as typical video frame rate, and lower-resolution imagery at a second frame rate, which is higher than the first rate. In one embodiment, the first frame rate data can be viewed by a user and the second frame rate data can be processed to identify an event of interest, such as pulsed light.

Methods And Apparatus For 3D Uv Imaging

US Patent:
2013027, Oct 24, 2013
Filed:
Apr 18, 2012
Appl. No.:
13/449637
Inventors:
Adam M. Kennedy - Santa Barbara CA, US
Michael D. Jack - Goleta CA, US
James Asbrock - Oceanside CA, US
Frank B. Jaworski - Goleta CA, US
Assignee:
RAYTHEON COMPANY - Waltham MA
International Classification:
H01L 27/146
H04N 13/02
US Classification:
348 42, 250372, 250395, 25037013, 977954, 348E13074
Abstract:
A 3D ultraviolet (UV) imaging LADAR system includes a UV source configured to generate a UV interrogation beam, a sensor configured to receive a UV return beam reflected from a target and to produce an electrical signal, and an imaging module coupled to the sensor and configured to receive the electrical signal and to generate a corresponding 3D image of the target. In one example, the sensor includes a down-shifting device configured to down-shift the UV return beam to a down-shifted light beam of a different wavelength, for example, in the visible or SWIR wavelength ranges.

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