James R Shealy, Age 67640 Highland Rd, Ithaca, NY 14850

James Shealy Phones & Addresses

640 Highland Rd, Ithaca, NY 14850

Hector, NY

Hendersonville, NC

Liverpool, NY

Mentions for James R Shealy

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Resumes

James Shealy Photo 22

Staff Electrical Engineer

Location:
Ithaca, NY
Work:
Odyssey Semiconductor
Staff Electrical Engineer
Education:
Cornell University 2012 - 2016
Bachelors, Bachelor of Science
James Shealy Photo 23

James Shealy

Location:
United States

Publications & IP owners

Us Patents

Single Step Process For Epitaxial Lateral Overgrowth Of Nitride Based Materials

US Patent:
6478871, Nov 12, 2002
Filed:
Oct 2, 2000
Appl. No.:
09/676938
Inventors:
James R. Shealy - Ithaca NY
Joseph A. Smart - Auburn NY
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
C30B 2504
US Classification:
117 84, 117 94, 117 95, 117951
Abstract:
An epitaxial deposition process produces epitaxial lateral overgrowth (ELO) of nitride based materials directly a patterned substrate ( ). The substrate ( ) is preferably formed from SiC or sapphire, and is patterned with a mask ( ), preferably formed of silicon nitride, having a plurality of openings ( ) formed therein. A nucleation layer ( ), preferably formed of AlGaN, is grown at a high reactor temperature of 700-1100 degrees C. , which wets the exposed substrate surface, without significant nucleation on the mask ( ). This eliminates the need for regrowth while producing smooth growth surfaces in the window openings ( ) as well as over the mask ( ). Subsequent deposition of a nitride based material layer ( ), preferably GaN, results in a relatively defect free planar surfaced material grown laterally over the mask ( ).

Single Step, High Temperature Nucleation Process For A Lattice Mismatched Substrate

US Patent:
7250360, Jul 31, 2007
Filed:
Mar 2, 2005
Appl. No.:
11/069040
Inventors:
James R. Shealy - Ithaca NY, US
Joseph A. Smart - Mooresville NC, US
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
H01L 21/28
H01L 21/3205
US Classification:
438603, 438604, 438607, 257E21097, 257E21108, 257E21112, 257E21118, 257E21126
Abstract:
A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.

Iii-V Semiconductor Structures Including Aluminum-Silicon Nitride Passivation

US Patent:
2012015, Jun 21, 2012
Filed:
Jun 28, 2010
Appl. No.:
13/380104
Inventors:
James R. Shealy - Ithaca NY, US
Richard Brown - Ithaca NY, US
Assignee:
CORNELL UNIVERSITY - Ithaca NY
International Classification:
H01L 29/16
H01L 29/778
H01L 29/78
H01L 29/20
US Classification:
257 77, 257183, 257 76, 257194, 257192, 257E29082, 257E29089, 257E29246, 257E29255
Abstract:
A semiconductor structure includes a semiconductor layer that is passivated with an aluminum-silicon nitride layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.

Method For Forming Iii-V Semiconductor Structures Including Aluminum-Silicon Nitride Passivation

US Patent:
2012015, Jun 21, 2012
Filed:
Jun 28, 2010
Appl. No.:
13/380150
Inventors:
James R. Shealy - Ithaca NY, US
Richard Brown - Ithaca NY, US
Assignee:
CORNELL UNIVERSITY - Ithaca NY
International Classification:
H01L 21/335
H01L 21/20
US Classification:
438172, 438478, 257E2109, 257E21403
Abstract:
A method for fabricating a semiconductor structure includes forming a semiconductor layer over a substrate and forming an aluminum-silicon nitride layer upon the semiconductor layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.

Chemical Vapor Deposition Process For Aluminum Silicon Nitride

US Patent:
2012015, Jun 21, 2012
Filed:
Jun 28, 2010
Appl. No.:
13/380144
Inventors:
James R. Shealy - Ithaca NY, US
Richard Brown - Ithaca NY, US
Assignee:
CORNELL UNIVERSITY - Ithaca NY
International Classification:
H01L 21/31
US Classification:
438786, 257E2124
Abstract:
A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6×10-11 to about 8×10-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.

Gated Iii-V Semiconductor Structure And Method

US Patent:
2013015, Jun 20, 2013
Filed:
Jun 22, 2011
Appl. No.:
13/389127
Inventors:
James R. Shealy - Ithaca NY, US
Richard Brown - Ithaca NY, US
Assignee:
CORNELL UNIVERSITY - Ithaca NY
International Classification:
H01L 29/778
H01L 29/66
US Classification:
257190, 438172
Abstract:
A gated III-V semiconductor structure and a method for fabricating the gated III-V semiconductor structure includes a threshold modifying dopant region within a III-V semiconductor barrier layer at the base of an aperture through a passivation layer that otherwise passivates the III-V semiconductor barrier layer. The passivation layer, which may comprise an aluminum-silicon nitride material, has particular bandgap and permittivity properties that provide for enhanced performance of a III-V semiconductor device that derives from the III-V semiconductor structure absent a field plate. The threshold modifying dopant region provides the possibility for forming both an enhancement mode gated III-V semiconductor structure and a depletion mode III-V semiconductor structure on the same substrate. The threshold modifying dopant region when comprising a magnesium (Mg) threshold modifying dopant may be incorporated into the gates III-V semiconductor structure using a dicyclopentadienyl magnesium (Cp2Mg) vapor diffusion method or a magnesium-silicon nitride (MgSiN) solid state diffusion method.

Process For Synthesis Of Cubic Gan On Gaas Using Nh.sub.3 In An Rf Plasma Process

US Patent:
5834379, Nov 10, 1998
Filed:
Jul 16, 1996
Appl. No.:
8/680874
Inventors:
James R. Shealy - Ithaca NY
James R. Engstrom - Ithaca NY
Yu-Hwa Lo - Ithaca NY
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
C23C 1108
US Classification:
438767
Abstract:
A process for synthesizing wide band gap materials, specifically, GaN, employs plasma-assisted and thermal nitridation with NH. sub. 3 to convert GaAs to GaN. Thermal assisted nitridation with NH. sub. 3 can be employed for forming layers of substantial thickness (on the order of 1 micron) of cubic and hexagonal GaN on a GaAs substrate. Plasma-assisted nitridation of NH. sub. 3 results in formation of predominantly cubic GaN, a form particularly useful in optoelectronic devices. Preferably, very thin GaAs membranes are employed to permit formation thereon of GaN layers of any desired thickness without concern for critical thickness constraints. The thin membranes are preferably formed either with an epitaxial bonding technique, or by undercut etching.

Synthetic Chamois Wiping Cloths

US Patent:
4341832, Jul 27, 1982
Filed:
May 29, 1981
Appl. No.:
6/268258
Inventors:
Gary A. Barnett - Lyman SC
James P. Shealy - Rock Hill SC
Assignee:
M. Lowenstein Corporation - New York NY
International Classification:
B32B 300
US Classification:
428196
Abstract:
An improved composite sheet material product having the appearance, drape, hand and water absorption and retention characteristics of natural chamois leather, comprising, in combination, a reinforcing textile fabric having opposed raised fiber faces, a soft water-absorbent porous polymeric foam layer secured to the opposed raised fibrous faces of the textile fabric, the foam layers having a normal high surface tack characteristic causing sticking and delamination of the layers from the sheet material under pressure contact, and wherein the exposed porous surfaces of the normally tacky foam layers are coated with a non-tacky water insoluble, film-forming polymer, such as a urethane polymer, to minimize tackification and delamination of the foam layers without noticeable loss in water absorption, retention, and appearance of the composite sheet material to that of natural chamois leather. Also disclosed is a method of manufacture of such composite sheet material products.

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