James Toner Sundby, Age 692970 Compton Pl, Tracy, CA 95377

7646224, Jan 12, 2010

May 4, 2007

11/744386

James Toner Sundby - Tracy CA, US

Exar Corporation - Fremont CA

H03L 7/06

327156, 327 18, 327147, 375373

A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.

7816958, Oct 19, 2010

May 4, 2007

11/744420

James Toner Sundby - Tracy CA, US

Exar Corporation - Fremont CA

H03L 7/06

327156, 327147, 327157, 327158, 327161

A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.

2008021, Sep 11, 2008

Mar 5, 2007

11/681886

James Toner Sundby - Tracy CA, US

Exar Corporation - Fremont CA

H03L 7/00

331 17

A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin.

2008021, Sep 11, 2008

Aug 2, 2007

11/833158

James Toner Sundby - Tracy CA, US

Exar Corporation - Fremont CA

H03L 7/06

331 17

A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin.

2010015, Jun 24, 2010

Nov 24, 2009

12/625406

James Toner Sundby - Tracy CA, US

Exar Corporation - Fremont CA

H03L 7/06

327156

A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.

5315264, May 24, 1994

May 10, 1993

8/060148

James T. Sundby - Tracy CA
Alexei N. Shkidt - Newark CA

Exar Corporation - San Jose CA

H03F 345

330253

A rail-to-rail CMOS operational amplifier with a large source current and small quiescent current. The CMOS opamp includes a folded cascode input structure, a negative slew detector and an output stage that acts as a push-pull output stage during slewing and a Class A output stage during small signal operation. The opamp can drive large capacitive loads (in excess of 0. 5. mu. F), with the load capacitor providing for the opamp frequency compensation.

5440254, Aug 8, 1995

Oct 20, 1992

7/963867

James T. Sundby - Tracy CA

Exar Corporation - San Jose CA

H03K 5153

327 79

An accurate and stable low voltage detect circuit that provides a low voltage detect signal with minimal variation over process and temperature without trimming requirements. The power supply voltage is divided by a resistor voltage divider and compared to the output voltage of a bandgap reference circuit at the inputs of a comparator. The output of the comparator indicates power-on when the voltage divided power supply raises above the bandgap reference voltage. The low voltage detect circuit of the present invention will generate a correct low voltage detect signal even at power supply voltages too low for much of the rest of the circuit to operate properly. At low enough Vcc voltages, a transistor switch disconnects the resistor voltage divider from Vcc, causing all voltages taps off of the resistor voltage divider to drop to ground. Additionally, especially designed bandgap reference and comparator circuits ensure proper operation of the low voltage detect circuit at low power supply voltages.

5325069, Jun 28, 1994

Dec 29, 1992

7/998153

James T. Sundby - Tracy CA

Exar Corporation - San Jose CA

H03F 345

330253

A CMOS opamp having large sinking and sourcing currents, and capable of driving high capacitive loads. The CMOS opamp improves a prior art OPAMP that includes a folded cascode gain stage and a class A/B output stage. By inserting a source follower stage between the folded cascode stage and the output stage, the opamp can drive very large capacitive loads that can also compensate the opamp. By further modifying the output stage, the ability to sink load current is vastly improved.