James F Testa, Age 40Kennett Square, PA

James Testa Phones & Addresses

Kennett Square, PA

8200 Kern Ave, Gilroy, CA 95020 (408) 846-9353

7535 Princevalle St, Gilroy, CA 95020 (408) 846-9353

Mentions for James F Testa

Professional Records

License Records

James A Testa

Licenses:
License #: 296728-6502 - Expired
Category: Burglar Alarm
Issued Date: Jul 27, 1993
Expiration Date: Jul 27, 1994
Type: Burglar Alarm Company Agent

James Francis Testa

Licenses:
License #: 6092 - Expired
Issued Date: Jan 29, 1981
Renew Date: May 31, 1996
Expiration Date: May 31, 1996
Type: Certified Public Accountant

James Testa

Licenses:
License #: 2705007433 - Expired
Category: Contractor
Issued Date: Feb 11, 1992
Expiration Date: Feb 29, 1996
Type: Class B

Publications

Us Patents

Low Power Data Latch With Overdriven Clock Signals

US Patent:
5568429, Oct 22, 1996
Filed:
Jul 5, 1995
Appl. No.:
8/498149
Inventors:
Godfrey P. D'Souza - San Jose CA
James F. Testa - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G11C 700
H03K 1756
US Classification:
36518905
Abstract:
A data latch with reduced data signal leakage includes a latch circuit and a clock buffer circuit which provides a differential clock signal to the input transmission gate of the latch circuit. The clock buffer circuit is biased between upper and lower supply voltage potentials which are higher and lower, respectively, than those between which the latch circuit is biased. This causes the differential clock signal to be overdriven with respect to the incoming data signal which is latched by the latch circuit. As a result, the input transmission gate of the latch circuit is reverse-biased during the inactive state of the differential clock signal, thereby isolating the storage node within the latch circuit and preventing signal leakage therefrom.

Modular Circuit Board Placement System

US Patent:
5260854, Nov 9, 1993
Filed:
May 14, 1992
Appl. No.:
7/882804
Inventors:
Vince Hileman - San Jose CA
Steven J. Furuta - Santa Clara CA
Clifford B. Willis - Tracy CA
Robert J. Lajara - San Jose CA
James Testa - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
H01R 2368
US Classification:
361736
Abstract:
A modular circuit board placement system is disclosed that provides for flexible placement of daughterboards, for minimal bus signal path lengths between motherboard and daughterboards, and for ease of installation and removal of daughterboards. The placement system employs dual height bus connectors, a stepped back panel, easy to engage and disengage dual height card retainers, filler panels that also function as module mounts, and multipurpose circuit card handles that facilitate removal of daughterboards. Daughterboards have a two-tier staggered arrangement above the motherboard. Each daughterboard has a signal transfer end that electrically connects to the motherboard through one of the dual height bus connectors, and a back panel connector end that couples to the back panel with an accessory connector or with a filler panel that functions as an electromagnetic interference shield. Dual height card retainers that require no tools to operate function as retaining means to prevent daughterboards from working lose from bus connectors during shipment. Multi-purpose circuit card handles are employed to facilitate installation and removal of daughterboards during field upgrade and field service, or to function as circuit card retainers in systems having only one tier of daughterboards.

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