Jason Sheu1183 Belbrook Way, Milpitas, CA 95035
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1183 Belbrook Way, Milpitas, CA 95035
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Us Patents
Processor Instruction Cache With Dual-Read Modes
US Patent:
8027218, Sep 27, 2011
Filed:
Apr 2, 2008
Appl. No.:
12/061296
Inventors:
Sehat Sutardja - Los Altos Hills CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Assignee:
Marvell World Trade Ltd. - St. Michaels
International Classification:
G11C 8/00
US Classification:
36523006, 365203, 365154, 365190
Abstract:
A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.
Processor Instruction Cache With Dual-Read Modes
US Patent:
8089823, Jan 3, 2012
Filed:
Aug 25, 2010
Appl. No.:
12/868341
Inventors:
Sehat Sutardja - Los Altos Hills CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
G11C 8/00
US Classification:
36523006, 36523009, 365203, 365204
Abstract:
A processor including a memory and a control module. The memory has an array of cells. The control module is configured to: determine a number of access cycles along a first word line; determine an extended period based on the number of the access cycles; generate a word line signal to maintain the first word line in an activated state during (i) an initial period and (ii) the extended period; and access a first cell during the extended period. The first cell is connected to the first word line. The control module is further configured to deactivate the word line and maintain the first word line in a deactivated state while accessing a second cell connected to the first word line. The accessing of the second cell is based on a bit line separation provided during the extended period.
Processor Instruction Cache With Dual-Read Modes
US Patent:
8295110, Oct 23, 2012
Filed:
Sep 26, 2011
Appl. No.:
13/245551
Inventors:
Sehat Sutardja - Los Altos Hills CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
G11C 7/00
US Classification:
365203, 3652331, 36523311, 711125, 712205
Abstract:
A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.
Processor With Memory Delayed Bit Line Precharging
US Patent:
8526257, Sep 3, 2013
Filed:
Oct 22, 2012
Appl. No.:
13/657502
Inventors:
- St. Michael, BB
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Los Altos Hills CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Los Altos Hills CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
G11C 7/00
US Classification:
365203, 3652331, 36523311, 711125, 712205
Abstract:
A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.
Processor Instruction Cache With Dual-Read Modes
US Patent:
2008016, Jul 10, 2008
Filed:
Oct 11, 2007
Appl. No.:
11/870833
Inventors:
Sehat Sutardja - Los Altos Hills CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US
International Classification:
G11C 7/00
G11C 8/00
G11C 8/00
US Classification:
365203, 36523001, 36523006
Abstract:
A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.
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