Jason Teller resumes & CV records
Resumes
Jason Teller
Jason Teller, Age 47Arcadia, CA
Jason Teller Phones & Addresses
Arcadia, CA
Waimanalo, HI
1051 National Ave APT 535, San Bruno, CA 94066
680 Mission St, San Francisco, CA 94105 (415) 341-1756
101 Crescent Ave, San Francisco, CA 94134 (415) 467-3685
1111 Makaiwa St, Honolulu, HI 96816
Palo Alto, CA
Cupertino, CA
Farley, MO
101 Crescent Way APT 2404, San Francisco, CA 94134 (415) 467-3685
Education
Degree:
High school graduate or higher
Mentions for Jason Teller
Publications & IP owners
Us Patents
Sharing Execution Logic
US Patent:
2020009, Mar 26, 2020
Filed:
Sep 21, 2018
Appl. No.:
16/138309
Inventors:
- San Francisco CA, US
Jason Teller - San Bruno CA, US
Miko Arnab Bose - San Francisco CA, US
Charles C. Reid - Alameda CA, US
Harsha Lingampally - San Francisco CA, US
Aaron Liang Bin Liu - San Jose CA, US
Joseph Leong - Apex NC, US
Alexander Frederick Schaffer - Dexter MI, US
Jason Teller - San Bruno CA, US
Miko Arnab Bose - San Francisco CA, US
Charles C. Reid - Alameda CA, US
Harsha Lingampally - San Francisco CA, US
Aaron Liang Bin Liu - San Jose CA, US
Joseph Leong - Apex NC, US
Alexander Frederick Schaffer - Dexter MI, US
International Classification:
G06Q 30/00
H04M 3/51
H04M 3/523
G06F 17/30
H04L 29/08
H04M 3/51
H04M 3/523
G06F 17/30
H04L 29/08
Abstract:
Disclosed are examples of systems, apparatuses, methods and computer program products for maintaining flows to manage tasks assigned to a user of a database system. Further disclosed are examples of systems, apparatuses, methods and computer program products for sharing execution logic, including but not limited to running instances of flows, across different users of a database system.
Processing A Sequence Of Operations Using Operation Tracking Screens
US Patent:
2020001, Jan 16, 2020
Filed:
Jul 16, 2018
Appl. No.:
16/036063
Inventors:
- San Francisco CA, US
Jason Teller - San Francisco CA, US
Nathan Edward Lipke - Denver CO, US
Anvitha Jaishankar - San Francisco CA, US
James Johnson - San Francisco CA, US
Yucheng Wang - San Mateo CA, US
Hugh Cockburn - San Francisco CA, US
Jason Teller - San Francisco CA, US
Nathan Edward Lipke - Denver CO, US
Anvitha Jaishankar - San Francisco CA, US
James Johnson - San Francisco CA, US
Yucheng Wang - San Mateo CA, US
Hugh Cockburn - San Francisco CA, US
International Classification:
G06F 3/0484
G06F 9/451
G06F 3/01
G06F 3/0483
G06F 17/30
G06F 9/451
G06F 3/01
G06F 3/0483
G06F 17/30
Abstract:
A processor can cause operation tracking screens to be presented on a display. The operation tracking screens can include first and second screen areas. Some of the first screen areas can have graphical control elements configured to receive information associated with actions associated with a sequence of operations. The actions can include first and second actions performed concurrently. The second screen areas can have a graphical representation of stages of the sequence of operations. The graphical representation of the stages can be of a default sequence of the stages, in response to an initiation of the sequence of operations, and can be modified to include a graphical representation of an additional stage in response to a determination of a result of a condition being a specific value. The processor can receive signals associated with the information associated with the actions and can cause the sequence of operations to be processed.
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