Jeffrey V Chamberlain, Age 622084 E Honeysuckle Pl, Chandler, AZ 85286

2021037, Dec 2, 2021

Aug 13, 2021

17/401575

- Santa Clara CA, US
Edwin VERPLANKE - Chandler AZ, US
Ravishankar IYER - Portland OR, US
Christopher GIANOS - Sterling MA, US
Jeffrey D. CHAMBERLAIN - Tracy CA, US
Ronak SINGH - Portland OR, US
Julius MANDELBLAT - Haifa, IL
Bret Toll - Hillsboro OR, US

G06Q 40/02
G06F 12/0875
G06F 12/0897

Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

2021026, Aug 26, 2021

Apr 16, 2019

17/255588

- Santa Clara CA, US
Kshitij Doshi - Tempe AZ, US
Andrew J. Herdrich - Hillsboro OR, US
Anup Mohan - Milpitas CA, US
Ravishankar R. Iyer - Portland OR, US
Mingqiu Sun - Beaverton OR, US
Krishna Bhuyan - Sammamish WA, US
Teck Joo Goh - Saratoga CA, US
Mohan J. Kumar - Aloha OR, US
Michael Prinke - Aloha OR, US
Michael Lemay - Hillsboro OR, US
Leeor Peled - Magal, IL
David M. Durham - Beaverton OR, US
Jeffrey D. Chamberlain - Tracy CA, US
Vadim A. Sukhomlinov - Santa Clara CA, US
Eric J. Dahlen - Sherwood OR, US
Sara Baghsorkhi - Los Gatos CA, US
Harshad Sane - Portland OR, US
Areg Melik-Adamyan - Austin TX, US
Ravi Sahita - Portland OR, US
Ian M. Steiner - Portland OR, US
Alexander Bachmutsky - Sunnyvale CA, US
Anil Rao - Menlo Park CA, US
Mingwei Zhang - Hillsboro OR, US
Nilesh K. Jain - Portland OR, US
Amin Firoozshahian - Mountain View CA, US
Baiju V. Patel - Portland OR, US
Wenyong Huang - Beijing, CN
Yeluri Raghuram - San Jose CA, US

Intel Corporation - Santa Clara CA

G06F 9/50
G06F 21/53
G06F 9/52
G06F 21/60
G06F 11/30
G06F 11/34

Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

2021007, Mar 11, 2021

Oct 30, 2020

17/086243

- Santa Clara CA, US
Omkar MASLEKAR - Chandler AZ, US
Priya AUTEE - Chandler AZ, US
Edwin VERPLANKE - Chandler AZ, US
Andrew J. HERDRICH - Hillsboro OR, US
Jeffrey D. CHAMBERLAIN - Tracy CA, US

G06F 12/0811
G06F 12/084
G06F 12/1009
G06F 9/30

Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

2018037, Dec 27, 2018

Jun 27, 2017

15/634785

- Santa Clara CA, US
Edwin Verplanke - Queen Creek AZ, US
Stephen R. Van Doren - Portland OR, US
Ravishankar Iyer - Hillsboro OR, US
Eric R. Wehage - Tenino WA, US
Rupin H. Vakharwala - Hillsboro OR, US
Rajesh M. Sankaran - Portland OR, US
Jeffrey D. Chamberlain - Dublin CA, US
Julius Mandelblat - Haifa, IL
Yen-Cheng Liu - Portland OR, US
Stephen T. Palermo - Chandler AZ, US
Tsung-Yuan C. Tai - Portland OR, US

G06F 12/0811
G06F 13/42
G06F 9/455
G06F 9/50
G06F 12/1009
G06F 13/16

Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

2017019, Jul 6, 2017

Jan 9, 2017

15/401220

- Santa Clara CA, US
Edwin Verplanke - Chandler AZ, US
Ravishankar Iyer - Portland OR, US
Christopher C. Gianos - Sterling MA, US
Jeffrey D. Chamberlain - Tracy CA, US
Ronak Singhal - Portland OR, US
Julius Mandelblat - Haifa, IL
Bret L. Toll - Hillsboro OR, US

G06F 12/0804
G06F 12/084
G06F 12/0897
G06F 12/0864
G06F 12/0875
G06F 12/0811
G06F 12/0842

Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

2016029, Oct 13, 2016

Apr 7, 2015

14/680287

- Santa Clara CA, US
EDWIN VERPLANKE - Chandler AZ, US
RAVISHANKAR IYER - Portland OR, US
CHRISTOPHER C. GIANOS - Sterling MA, US
JEFFREY D. CHAMBERLAIN - Tracy CA, US
RONAK SINGHAL - Portland OR, US
JULIUS MANDELBLAT - Haifa, IL
BRET L. TOLL - Hillsboro OR, US

G06F 12/08

Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.