Jeffrey Su9621 Rainlilly Ln, Austin, TX 78759

6574160, Jun 3, 2003

Feb 11, 2002

10/074396

Nadeem N. Eleyan - Austin TX
Howard L. Levy - Cedar Park TX
Jeffrey Y. Su - Cedar Park TX

Sun Microsystems, Inc. - Santa Clara CA

G11C 702

365207, 365205, 36523006

According to one embodiment, a memory is disclosed. The memory includes a differential sense amplifier that receives a data input and a complementary data input; and a switching mechanism, coupled to the amplifier, that switches the data input and the complementary data input to minimize a negative bias temperature instability (NBTI) effect on the amplifier.

6762961, Jul 13, 2004

Apr 16, 2002

10/123480

Nadeem N. Eleyan - Austin TX
Howard L. Levy - Cedar Park TX
Jeffrey Y. Su - Cedar Park TX

Sun Microsystems, Inc. - Sunnyvale CA

G11C 700

365194, 365201, 365207

Post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit. One particular example of such data-dependent degradation or creep involves Negative Bias Temperature Instability (NBTI). In certain memory circuit configurations, NBTI can cause threshold voltage (V ) of PMOS devices to increase by an amount that depends on the historical amount of voltage bias that has been applied across gate and source/drain nodes. In the case of many sense amplifier designs, a predominant value read out using the sense amp may tend to disparately affect one device (or set of devices) as compared with an opposing device (or set of devices). In other words, if the same data value is read over and over again, then one of two opposing PMOS devices of a typical sense amp will accumulate an NBTI-related V shift, while the opposing PMOS device will accumulate little or no shift. The accumulated mismatch tends to cause an increase in the sense amp fail-point.

7020035, Mar 28, 2006

Oct 10, 2003

10/683633

Nadeem N. Eleyan - Austin TX, US
Howard L. Levy - Cedar Park TX, US
Jeffrey Y. Su - Cedar Park TX, US

Sun Microsystems, Inc. - Santa Clara CA

G11C 7/02

365207, 365210, 3652335

Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. Such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, purposefully skewed values (e. g. , value and value_1) are introduced directly into the sense amplifier. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch.

7164612, Jan 16, 2007

Oct 10, 2003

10/683636

Nadeem N. Eleyan - Austin TX, US
Howard L. Levy - Cedar Park TX, US
Jeffrey Y. Su - Cedar Park TX, US

Sun Microsystems, Inc. - Santa Clara CA

G11C 7/00

365201, 365205

Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. In designs susceptible to post-manufacture data dependent creep in a device characteristic, such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch. Typically, the techniques described herein may be employed to address sensing offsets that have developed post-manufacture due to a data-dependent effect. However, in some realizations, the techniques described herein may be used to address a sensing offset arising at least in part from other or additional sources.

5754482, May 19, 1998

Apr 21, 1997

8/845097

Jeffrey Yangming Su - Cedar Park TX
Bruce Lee Morton - Austin TX
Chad Steven Gallun - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 1604

36518907

A memory (400) returns all bit lines to a predetermined voltage level optimum for subsequent fast sensing. The memory (400) includes precharge circuitry (106, 108, 110) which begins the precharge operation during the latching phase of a prior access. The precharge circuitry (106, 108, 110) precharges all bit lines, rather than a selected bit line, to the predetermined voltage level prior to address decoding. In order to prevent "walk-up", the memory (400) includes circuitry such as a switched capacitor (138, 140) which draws current from the bit lines to reduce the voltage on a bit line which drove a logic high level in an earlier cycle or which had an increased voltage due to capacitive cross-coupling to an adjacent bit line. The memory (400) may also include devices such as transmission gates (142, 144, 146) to couple together adjacent bit lines and thereby more evenly distribute the precharging.