Jennifer Elisa Morrison, Age 457935 E Posada Ave, Mesa, AZ 85212

6828650, Dec 7, 2004

May 31, 2002

10/160940

Patrice Parris - Phoenix AZ
Richard J De Souza - Tempe AZ
Jennifer H. Morrison - Chandler AZ
Moaniss Zitouni - Gilbert AZ
Xin Lin - Chandler AZ

Motorola, Inc. - Schaumburg IL

H01L 2900

257518, 257378, 257514, 257565

A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

7078785, Jul 18, 2006

Sep 23, 2003

10/668694

Anthony Ciancio - Gilbert AZ, US
Mark D. Griswold - Chandler AZ, US
Amudha R. Irudayam - Chandler AZ, US
Jennifer H. Morrison - Chandler AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 29/00
H01L 29/76
H01L 29/94

257532, 257306

By forming a conductive smoothing layer over the bottom electrode and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, layer including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer formed of a refractory nitride. In addition, a second refractory metal or a refractory metal-rich nitride layer may be formed on the capacitor dielectric. The smoothing layer could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.

7211477, May 1, 2007

May 6, 2005

11/124469

Edouard D. de Frésart - Tempe AZ, US
Richard J. De Souza - Tempe AZ, US
Xin Lin - Phoenix AZ, US
Jennifer H. Morrison - Chandler AZ, US
Patrice M. Parris - Phoenix AZ, US
Moaniss Zitouni - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/336
H01L 21/8234

438197, 438223, 438301

Methods and apparatus are provided for a MOSFET () exhibiting increased source-drain breakdown voltage (BVdss). Source (S) () and drain (D) () are spaced apart by a channel () underlying a gate () and one or more carrier drift spaces (′) serially located between the channel () and the source (′) or drain (′). A buried region (′) of the same conductivity type as the drift space (′) and the source (′) or drain (′) is provided below the drift space (′), separated therefrom in depth by a narrow gap (′) and ohmically coupled to the source (′) or drain (′). Current flow () through the drift space produces a potential difference (Vt) across this gap (′). As the S-D voltage (Vo) and current (, Io) increase, this difference (Vt) induces high field conduction between the drift space (′) and the buried region (′) and diverts part (, It) of the S-D current (, Io) through the buried region (′) and away from the near surface portions of the drift space (′) where breakdown generally occurs. Thus, BVdss is increased.

7301187, Nov 27, 2007

Mar 21, 2007

11/689313

Edouard D. Defresart - Tempe AZ, US
Richard J. Desouza - Tempe AZ, US
Xin Lin - Phoenix AZ, US
Jennifer H. Morrison - Chandler AZ, US
Patrice M. Parris - Phoenix AZ, US
Moaniss Zitouni - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

257288, 257341, 257401, 257E2913

Methods and apparatus are provided for a MOSFET () exhibiting increased source-drain breakdown voltage (BVdss). Source (S) () and drain (D) () are spaced apart by a channel () underlying a gate () and one or more carrier drift spaces (′) serially located between the channel () and the source (′) or drain (′). A buried region (′) of the same conductivity type as the drift space (′) and the source (′) or drain (′) is provided below the drift space (′), separated therefrom in depth by a narrow gap (′) and ohmically coupled to the source (′) or drain (′). Current flow () through the drift space produces a potential difference (Vt) across this gap (′). As the S-D voltage (Vo) and current (, Io) increase, this difference (Vt) induces high field conduction between the drift space (′) and the buried region (′) and diverts part (, It) of the S-D current (, Io) through the buried region (′) and away from the near surface portions of the drift space (′) where breakdown generally occurs. Thus, BVdss is increased.

7528015, May 5, 2009

Jun 28, 2005

11/169962

Patrice M. Parris - Phoenix AZ, US
Weize Chen - Phoenix AZ, US
John M. McKenna - Chandler AZ, US
Jennifer H. Morrison - Chandler AZ, US
Moaniss Zitouni - Gilbert AZ, US
Richard J. De Souza - Tempe AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/82
H01L 21/44
H01L 21/31

438131, 438600, 438770, 438981, 257E21625

A tunable antifuse element () and method of fabricating the tunable antifuse element, including a substrate material () having an active area () formed in a surface, a gate electrode () having at least a portion positioned above the active area (), and a dielectric layer () disposed between the gate electrode () and the active area (). The dielectric layer () including the fabrication of one of a tunable stepped structure (). During operation, a voltage applied between the gate electrode () and the active area () creates a current path through the dielectric layer () and a rupture of the dielectric layer () in a plurality of rupture regions (). The dielectric layer () is tunable by varying the stepped layer thicknesses and the geometry of the layer.

7700996, Apr 20, 2010

Jan 29, 2009

12/361944

Patrice M. Parris - Phoenix AZ, US
Weize Chen - Phoenix AZ, US
John M. McKenna - Chandler AZ, US
Jennifer H. Morrison - Chandler AZ, US
Moaniss Zitouni - Gilbert AZ, US
Richard J. De Souza - Tempe AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 29/94

257324, 257529, 257530, 257E29135, 257E29255

A tunable antifuse element () includes a substrate material () having an active area () formed in a surface, a gate electrode () having at least a portion positioned above the active area (), and a dielectric layer () disposed between the gate electrode () and the active area (). The dielectric layer () includes a tunable stepped structure (). During operation, a voltage applied between the gate electrode () and the active area () creates a current path through the dielectric layer () and a rupture of the dielectric layer () in a rupture region (). The dielectric layer () is tunable by varying the stepped layer thicknesses and the geometry of the layer.

2004007, Apr 22, 2004

Oct 16, 2002

10/272336

Moaniss Zitouni - Gilbert AZ, US
Edouard de Fresart - Tempe AZ, US
Richard De Souza - Tempe AZ, US
Xin Lin - Phoenix AZ, US
Jennifer Morrison - Chandler AZ, US
Patrice Parris - Phoenix AZ, US

Motorola, Inc.

H01L023/62
H01L021/336

257/355000, 257/358000, 257/375000, 438/298000, 438/450000

A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

2006013, Jun 22, 2006

Dec 17, 2004

11/015110

Patrice Parris - Phoenix AZ, US
Edouard de Fresart - Tempe AZ, US
Richard De Souza - Tempe AZ, US
Jennifer Morrison - Chandler AZ, US

H01L 21/336

438257000

A non-volatile memory bitcell structure is disclosed that includes a dual capacitor structure. A first metal-insulator-metal (MIM) capacitor having a first capacitance value includes a first top plate, a first bottom plate, and a first dielectric disposed in-between the first top plate and the first bottom plate. A second metal-insulator-metal (MIM) capacitor having a second capacitance value includes a second top plate, a second bottom plate, and a second dielectric disposed in-between the second top plate and the second bottom plate. An element of the first MIM capacitor is electrically coupled in common with an element of the second MIM capacitor. In addition, the first capacitance value is greater than the second capacitance value.