Jim Lin, Age 5312 Candlelight Ln, Lafayette, CA 94549

Jim Lin Phones & Addresses

12 Candlelight Ln, Lafayette, CA 94549 (925) 465-5053

40 Greentree Ct, Lafayette, CA 94549 (925) 299-9272

120 La Casa Via, Walnut Creek, CA 94598 (925) 299-9272

35 Severance Cir #724, Cleveland, OH 44118 (216) 752-5028

Cleveland Heights, OH

Chicago, IL

Portland, OR

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Work

Company: Foothill-de anza community college district Address: 4000 Middlefield Rd Ste I, Palo Alto, CA 94303 Position: Co ordinator program Industries: Junior Colleges and Technical Institutes

Education

School / High School: University Of Chicago/The Pritzker School Of Medicine 1991

Languages

English • Chinese, Min Nan

Awards

Healthgrades Honor Roll

Ranks

Certificate: Anesthesiology, 1998

Mentions for Jim Lin

Professional Records

Medicine Doctors

Jim Lin Photo 1

Dr. Jim Lin, Vallejo CA - MD (Doctor of Medicine)

Specialties:
Anesthesiology
Address:
975 Sereno Dr, Vallejo, CA 94589
(707) 651-1000 (Phone)
Certifications:
Anesthesiology, 1998
Awards:
Healthgrades Honor Roll
Languages:
English
Chinese, Min Nan
Education:
Medical School
University Of Chicago/The Pritzker School Of Medicine
Graduated: 1991
Medical School
University Hosps Cleveland
Graduated: 1992
Medical School
Oreg Health Scis University Hospital
Graduated: 1994
Medical School
University Chicago Hosps
Graduated: 1997
Medical School
University Hosps Cleveland
Graduated: 1993
Medical School
University Chicago Hosps
Graduated: 1998
Jim Lin Photo 2

Jim C Lin, Vallejo CA

Specialties:
Anesthesiology
Internal Medicine
Work:
Vallejo Medical Center
975 Sereno Dr, Vallejo, CA 94589
Education:
University of Chicago (1991)
Jim Lin Photo 3

Jim Lin, Vallejo CA

Specialties:
Anesthesiologist
Address:
975 Sereno Dr, Vallejo, CA 94589
Education:
University of Chicago, Pritzker School of Medicine - Doctor of Medicine
Bernard Mitchell Hospital-University of Chicago Hospitals - Fellowship - Neuroanesthesiology
Bernard Mitchell Hospital-University of Chicago Hospitals - Residency - Anesthesiology
OHSU Hospitals & Clinics - Residency - Internal Medicine
University Hospitals - Case Medical Center - Residency - Internal Medicine
Board certifications:
American Board of Anesthesiology Certification in Anesthesiology

Business Records

Name / TitleCompany / ClassificationPhones & Addresses
Jim Lin
Co Ordinator Program
Foothill-De Anza Community College District
Junior Colleges and Technical Institutes
4000 Middlefield Rd Ste I, Palo Alto, CA 94303
Jim C. Lin Jim Lin MD 975 Sereno Dr, Vallejo, CA 94589
(707) 651-1000

Publications

Us Patents

Data Exchange And Communication Between Execution Units In A Parallel Processor

US Patent:
8024553, Sep 20, 2011
Filed:
Aug 15, 2008
Appl. No.:
12/192813
Inventors:
Brucek Khailany - San Francisco CA,
William James Dally - Stanford CA,
Ujval J. Kapasi - San Jose CA,
Jim Jian Lin - Saratoga CA,
Assignee:
Calos Fund Limited Liability Company - Dover DE
International Classification:
G06F 9/44
G06F 15/76
US Classification:
712225, 712 33
Abstract:
A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

Data Exchange And Communication Between Execution Units In A Parallel Processor

US Patent:
8412917, Apr 2, 2013
Filed:
Sep 20, 2011
Appl. No.:
13/237646
Inventors:
Brucek Khailany - San Francisco CA,
William James Dally - Stanford CA,
Ujval J. Kapasi - San Jose CA,
Jim Jian Lin - Saratoga CA,
Assignee:
Calos Fund Limited Liability Company - Dover DE
International Classification:
G06F 9/00
US Classification:
712225
Abstract:
Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer paths are dynamically determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. In addition, embodiments include an integrated-circuit processing device operable to execute operations in parallel, including the capability of providing confirmation information to potential source lanes, the confirmation information indicating whether the potential source lanes may send data to requested destination lanes during a data-transfer interval.

Data-Parallel Processing Unit

US Patent:
2008014, Jun 12, 2008
Filed:
Oct 9, 2007
Appl. No.:
11/973887
Inventors:
Brucek Khailany - San Francisco CA,
William James Dally - Stanford CA,
Ujval J. Kapasi - San Jose CA,
Jim Jian Lin - Saratoga CA,
Raghunath Rao - Austin TX,
DeForest Tovey - Los Gatos CA,
Mark Rygh - Union City CA,
Jung-Ho Ahn - Palo Alto CA,
International Classification:
G06F 9/30
G06F 9/302
US Classification:
712205, 712225, 712221, 712E09016, 712E09017
Abstract:
A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

Tracing Command Execution In A Parallel Processing System

US Patent:
2008030, Dec 4, 2008
Filed:
Aug 15, 2008
Appl. No.:
12/192885
Inventors:
Brucek Khailany - San Francisco CA,
Mark Rygh - Union City CA,
Jim Jian Lin - Saratoga CA,
Udo Uebel - San Francisco CA,
International Classification:
G06F 9/30
US Classification:
712227, 712E09016
Abstract:
Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory.

Isbn (Books And Publications)

Magic: The Gathering The Pocket Players' Guidefor Magic The Gathering

Author:
Jim Lin
ISBN #:
0061056235

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