Jim D Lin, Age 5912 Candlelight Ln, Lafayette, CA 94549

6775756, Aug 10, 2004

Oct 11, 1999

09/416196

Shalesh Thusoo - Milpitas CA
Niteen Patkar - Sunnyvale CA
Jim Lin - Sunnyvale CA

ATI International Srl - Barbados

G06F 1200

711169, 711140, 711215, 711214, 712219

A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.

7826450, Nov 2, 2010

Apr 25, 2005

11/114734

Jim Lin - Sunnyvale CA, US
Vijayasimha Kadamby - Fremont CA, US

Infineon Technologies AG - Neubiberg

H04L 12/28

370390, 370432

A method and system for routing a multicast packet through a unicast packet switch network of devices. A virtual destination group, which includes destination devices of the multicast packet, is defined, and then the virtual destination group is mapped to an unused unicast destination encoding in routing tables of the devices. The multicast packet is then routed from a source device to the destination devices using the routing tables.

8024553, Sep 20, 2011

Aug 15, 2008

12/192813

Brucek Khailany - San Francisco CA, US
William James Dally - Stanford CA, US
Ujval J. Kapasi - San Jose CA, US
Jim Jian Lin - Saratoga CA, US

Calos Fund Limited Liability Company - Dover DE

G06F 9/44
G06F 15/76

712225, 712 33

A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

8412917, Apr 2, 2013

Sep 20, 2011

13/237646

Brucek Khailany - San Francisco CA, US
William James Dally - Stanford CA, US
Ujval J. Kapasi - San Jose CA, US
Jim Jian Lin - Saratoga CA, US

Calos Fund Limited Liability Company - Dover DE

G06F 9/00

712225

Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer paths are dynamically determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. In addition, embodiments include an integrated-circuit processing device operable to execute operations in parallel, including the capability of providing confirmation information to potential source lanes, the confirmation information indicating whether the potential source lanes may send data to requested destination lanes during a data-transfer interval.

2008014, Jun 12, 2008

Oct 9, 2007

11/973887

Brucek Khailany - San Francisco CA, US
William James Dally - Stanford CA, US
Ujval J. Kapasi - San Jose CA, US
Jim Jian Lin - Saratoga CA, US
Raghunath Rao - Austin TX, US
DeForest Tovey - Los Gatos CA, US
Mark Rygh - Union City CA, US
Jung-Ho Ahn - Palo Alto CA, US

G06F 9/30
G06F 9/302

712205, 712225, 712221, 712E09016, 712E09017

A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

2008014, Jun 12, 2008

Oct 9, 2007

11/973895

Peter Mattson - Sunnyvale CA, US
Timothy J. Southgate - Woodside CA, US
Brucek Khailany - San Francisco CA, US
Mark Rygh - Union City CA, US
Jim Jian Lin - Saratoga CA, US
Raghunath Rao - Austin TX, US
Kenneth Hesky - Sunnyvale CA, US
Udo Uebel - San Francisco CA, US

G06F 12/02
G06F 13/00
G06F 1/10
G06F 12/00
G06F 9/46

719313, 711154, 713600, 711100, 718102, 711E12001, 711E12002

Within a data processing system, a user-entered data declaration within a program source file is inspected to determine whether a first qualifier is provided with or omitted from the user-entered data declaration. If the first qualifier is provided, an unreserved data storage location disposed within a data-processing integrated-circuit (IC) device is identified and allocated for storage of data associated with the user-entered data declaration.

2008030, Dec 4, 2008

Aug 15, 2008

12/192885

Brucek Khailany - San Francisco CA, US
Mark Rygh - Union City CA, US
Jim Jian Lin - Saratoga CA, US
Udo Uebel - San Francisco CA, US

G06F 9/30

712227, 712E09016

Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory.