Joel F Boney Deceased4529 Eagle Lake Dr, Fort Collins, CO 80524

6446224, Sep 3, 2002

Mar 3, 1995

08/397910

Chih-Wei David Chang - Saratoga CA
Joel Frederick Boney - Cupertino CA
Jaspal Kohli - Sunnyvale CA

Fujitsu Limited

H02H 305

714 54, 714 47, 714 43

A computer system includes a central processing unit and a memory management unit having a plurality of functional units, such as a memory interface unit, a remote interface unit, a cache interface unit, and a translation unit. Each functional unit has a low priority error queue for storing error information for errors having a low priority. Some functional units also have a high priority error queue for storing error information for errors having a high priority error. Based on the status of the error queues, the memory management unit prioritizes and handles errors caused by hardware failures. For low priority errors, an interrupt request signal is sent to the central processing unit. For high priority errors, a RED ALERT signal is sent to the processing unit to cause the processing unit to give immediate attention to the error. For high priority error queue overflows, a failure signal is generated which causes the system to be halted and the contents of the system to be scanned out. Thus, errors are prioritized and handled accordingly.

5835962, Nov 10, 1998

Dec 24, 1996

8/772835

Chih-Wei David Chang - Saratoga CA
Kioumars Dawallu - San Jose CA
Joel F. Boney - Cupertino CA
Ming-Ying Li - Sunnyvale CA

Fujitsu Limited

G06F 1210
G06F 922

711206

A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.

4573117, Feb 25, 1986

Nov 7, 1983

6/549957

Joel F. Boney - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 104

364200

A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The processor thus proceeds to the next instruction as if the power-down instruction were a "no-operation" instruction.

4250546, Feb 10, 1981

Jul 31, 1978

5/929482

Joel F. Boney - Austin TX
Fuad H. Musa - Austin TX
Terry F. Ritter - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 946

364200

A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.

4334268, Jun 8, 1982

May 1, 1979

6/035138

Joel F. Boney - Austin TX
Edward J. Rupp - Austin TX
James S. Thomas - Manor TX

Motorola, Inc. - Schaumburg IL

G06F 932

364200

A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the instruction set of the microcomputer are a branch on bit set instruction and a branch on bit clear instruction. The branch on bit set instruction is a three-byte instruction in which the first byte represents the op code including a designation of a particular bit to be examined, the second byte represents the address of a memory location in which the designated bit is to be examined, and the third byte represents an offset which when combined with the contents of the program counter designates a memory location to which a branch is to be taken if the designated bit is in fact set. For the branch on bit clear instruction, a branch is performed when the particular bit examined is determined not to be set. The branch on bit set and branch on bit clear instructions facilitate serial I/O operations by the microcomputer.

4683546, Jul 28, 1987

Oct 14, 1986

6/918682

Joel F. Boney - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 748

364748

A method and apparatus for generating floating point condition codes by using the data type of a result operand, rather than a magnitude relationship between two operands. The condition codes may then be combined to generate relations useful for identifying conditions for conditional branches or traps.