Johnny W Chan, Age 60Milpitas, CA

6856557, Feb 15, 2005

May 30, 2003

10/452562

Johnny Chan - Fremont CA, US
Jinshu Son - Saratoga CA, US
Ken Kun Ye - Fremont CA, US
Tinwai Wong - Fremont CA, US

Atmel Corporation - San Jose CA

G11C011/34

365190, 365233

A signal integrity checking circuit for an integrated circuit detects whether signal condition involving loading of data into storage elements is valid or improper and flags the result. The integrity circuit includes a plurality of adjacently positioned and substantially similar storage elements, which are clocked by a common clock line and loaded from a common data input line. A common reset line may also be provided. The storage elements may be flip-flops, latches, RAM, etc. A logic gate, such as a NAND gate, receives the storage element outputs and flags improper loading of data. Inverters on the input and output sides of one storage element force it to the opposite state from the other storage element. The signal integrity checking circuit is valuable for ensuring proper loading during power-on or start-up, and at other times when loading of data may occur.

6891917, May 10, 2005

Aug 4, 2003

10/634596

Johnny Chan - Fremont CA, US
Jeff Ming-Hung Tsai - Santa Clara CA, US
Philip S. Ng - Cupertino CA, US

Atmel Corporation - San Jose CA

G11C019/00

377 78, 377 79, 377 80, 377 81, 377 69

A shift register device includes transistor pass gates and latches connected in series and disposed along a data bit line, each latch connected to a corresponding transistor pass gate. Each transistor pass gate is controlled by a separate control signal input line that a provides a signal to the transistor pass gate connected to it. The signals are provided in a staggered time pattern beginning with a latch disposed last in succession, shifting data from one position to the next succeeding position. Each latch is capable of storing one bit of data. The shift register utilizes less silicon space while reducing the amount of power consumed during operation.

6937569, Aug 30, 2005

May 21, 2001

09/862049

Shantanu Sarkar - San Jose CA, US
Steven G. Fry - Oakland CA, US
Johnny C. Chan - San Francisco CA, US

Cisco Technology, Inc. - San Jose CA

G01R031/08

370238, 370252, 370519

A method and system for determining a relative location of a device on a network is provided. In this system and method, a list of landmark nodes provided on the network is received. Then, a value which is a time, a latency and/or a distance from the device to each of the landmark nodes is determined. Each of the determined values corresponding to the respective node of the landmark nodes is transmitted to a central arrangement to provide the relative location of the device with respect to the landmark nodes.

6998884, Feb 14, 2006

Dec 31, 2003

10/749342

Philip S. Ng - Cupertino CA, US
Jeff Ming-Hung Tsai - Santa Clara CA, US
Johnny Chan - Fremont CA, US

Atmel Corporation - San Jose CA

H03L 7/00

327143, 327198

An auto-grounding circuit responsive to a reset signal discharges an input terminal of an integrated circuit and its associated input line to ground, using a pull-down transistor coupled to the input line, with a gate of the pull-down transistor coupled to receive the reset signal. An exemplary circuit also includes a NAND gate and a second pull-down transistor to maintain an established voltage level of the input line after the reset signal is no longer asserted until the input terminal is driven by an applied input signal. The voltage maintaining circuitry is weaker than the main pull-down transistor to avoid interfering with normal operation of the input terminal.

7082490, Jul 25, 2006

Oct 20, 2003

10/690082

Johnny Chan - Fremont CA, US
Philip S. Ng - Cupertino CA, US
Tinwai Wong - Fremont CA, US

Atmel Corporation - San Jose CA

G06F 12/00

711103, 711156, 711154, 36518533

An integrated circuit device includes a plurality of non-volatile memory cells associated with a plurality of flag cells storing managing data. The managing data of the flag cells forms a data set. The data set is utilized to determine to which memory cell of the plurality of memory cells to write new data and from which of the memory cells to read currently stored data. The data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next. The data set may be changed by alternately writing a new value to a different flag cell in each successive change of the data set.

7145318, Dec 5, 2006

Nov 21, 2005

11/284779

Johnny Chan - Fremont CA, US
Tin Wai Wong - Fremont CA, US
Ken Kun Ye - Femont CA, US

Atmel Corporation - San Jose CA

G05F 3/16
G05F 1/40

323316, 323280, 327539

A first voltage divider includes a first resistor having a first resistance coupled to a positive voltage reference in series with a second resistor having a second resistance and coupled to ground. A second voltage divider includes a third resistor having the first resistance coupled to the positive voltage potential in series with a fourth resistor having the second resistance, and a fifth resistor having a third resistance and coupled to a negative voltage. A comparator has an inverting input coupled to the junction of the first and second resistors and a non-inverting input coupled to the junction of the third and fourth resistors. The first and third resistors are equal and the second and fourth resistors are equal. The fifth resistor has a value chosen to drop a voltage equal to the target voltage to be regulated when the voltage regulator output is equal to that target voltage.

7180795, Feb 20, 2007

Aug 5, 2005

11/198469

Johnny Chan - Fremont CA, US
Jinshu Son - Saratoga CA, US
Philip S. Ng - Cupertino CA, US

Atmel Corporation - San Jose CA

G11C 5/14

36518909, 16518904

An array of memory cells having a predetermined group of storage cells, arranged in a row, also have an arrangement of one or more reference cells fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the storage cells are written to, erased, or programmed. The same number of write, erase, or program cycles and the proximity of the reference cells to the storage cells maintain an operational matching of the storage cells and reference cells.

7233528, Jun 19, 2007

Jul 25, 2005

11/188612

Johnny Chan - Fremont CA, US
Jeffrey Ming-Hung Tsai - San Jose CA, US

Atmel Corporation - San Jose CA

G11C 16/04

36518528, 36518518, 36518533

A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data “one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data “zero” is to be applied to the bit cell, a charge pump engages to bias the cell and activate a hot electron injection process to affect the programming. If a data “one” is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell in the data structure. Therefore, total programming time is reduced proportionally to the number of data “one” bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, total programming time is further reduced when two data “one” values are to be programmed in parallel.