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John T Yue Deceased32926 Great Salt Lake Dr, Fremont, CA 94555

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Related to:
Chunrong Yan 43

John Yue Phones & Addresses

32926 Great Salt Lake Dr, Fremont, CA 94555

Oakland, CA

Union City, CA

Alameda, CA

Work

Address: 39962 Cedar Blvd # 222, Newark, CA 94560 Specialities: Corporate / Incorporation - 50% • Mergers / Acquisitions - 30% • Venture Capital - 20%

Education

Degree: law School / High School: Golden Gate Univ SOL

Ranks

Licence: California - Active Date: 1994

Mentions for John T Yue

Career records & work history

Lawyers & Attorneys

John Yue Photo 1

John Qiang Yue, Newark CA - Lawyer

Address:
39962 Cedar Blvd # 222, Newark, CA 94560
(510) 931-6162 (Office)
Licenses:
California - Active 1994
Education:
Golden Gate Univ SOLDegree law
Specialties:
Corporate / Incorporation - 50%
Mergers / Acquisitions - 30%
Venture Capital - 20%
Languages:
Mandarin, Vietnamese
Description:
Experienced international attorney and registered foreign lawyer in Vietnam advising clients on Vietnam market entry, FDI, cross-border MA, labor employment,...
John Yue Photo 2

John Q. Yue, Newark CA - Lawyer

Office:
39962 Cedar Blvd., Ste. 222, Newark, CA
Specialties:
Corporations, Immigration, International Business Transactions
ISLN:
911761687
Admitted:
1994
Law School:
Golden Gate University, J.D.
John Yue Photo 3

John Yue - Lawyer

Resumes & CV records

Resumes

John Yue Photo 32

John Yue

Location:
New York, New York
Industry:
Design
Languages:
English
Chinese
John Yue Photo 33

Vice President At Omnivision Technologies

Position:
Vice President at OmniVision Technologies, VP QR at OVT
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
OmniVision Technologies
Vice President OVT since 2005
VP QR
John Yue Photo 34

John Yue

Location:
United States

Publications & IP owners

Us Patents

Apparatus And Method For Testing Image Sensor Wafers To Identify Pixel Defects

US Patent:
8000520, Aug 16, 2011
Filed:
Nov 28, 2007
Appl. No.:
11/946265
Inventors:
Chia-Lun Chang - Sunnyvale CA, US
Chih-huei Wu - San Jose CA, US
John T. Yue - Los Altos CA, US
Assignee:
OmniVision Technologies, Inc. - Santa Clara CA
International Classification:
G06K 9/00
G01N 21/00
H04N 17/00
H04N 17/02
G01C 25/00
US Classification:
382149, 3562375, 348187, 702116
Abstract:
An image sensor testing apparatus is disclosed. The image sensor testing apparatus includes an electronic test system having a light source for illuminating an image sensor wafer to generate pixel data and a host processor for receiving the pixel data. An interface card coupled to the electronic test system has a programmable processor for processing the pixel data to generate processed data, the processed data transmitted to and analyzed by the host processor together with the pixel data to detect pixel defects in the image sensor wafer.

Bar Field Effect Transistor

US Patent:
6180441, Jan 30, 2001
Filed:
May 10, 1999
Appl. No.:
9/307698
Inventors:
John T. Yue - Los Altos CA
Matthew S. Buynoski - Palo Alto CA
Yowjuang W. Liu - San Jose CA
Peng Fang - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
H01L 218234
H01L 2122
US Classification:
438197
Abstract:
A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Bar Field Effect Transistor

US Patent:
5932911, Aug 3, 1999
Filed:
Dec 13, 1996
Appl. No.:
8/766494
Inventors:
John T. Yue - Los Altos CA
Matthew S. Buynoski - Palo Alto CA
Yowjuang W. Liu - San Jose CA
Peng Fang - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2976
H01L 2994
H01L 31062
US Classification:
257330
Abstract:
A field effect transistor is formed across one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Test Method For Predicting Hot-Carrier Induced Leakage Over Time In Short-Channel Igfets And Products Designed In Accordance With Test Results

US Patent:
5606518, Feb 25, 1997
Filed:
May 16, 1995
Appl. No.:
8/442320
Inventors:
Hao Fang - Cupertino CA
Peng Fang - Milpitas CA
John T. Yue - Los Altos CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 19145
G01R 3128
US Classification:
364578
Abstract:
A test method and apparatus are provided for predicting hot-carrier induced leakage over time in IGFET's. Test results are used to show how choice of channel length and stress voltages critically affect hot-carrier-induced leakage (HCIL) leakage over time, particularly in devices having submicron channel lengths. Models are developed for predicting leakage current over the long term given short term test results. Alternative design strategies are proposed for reliably satisfying long term leakage requirements.

Void Detection In Metallization Patterns

US Patent:
5504017, Apr 2, 1996
Filed:
Dec 20, 1994
Appl. No.:
8/359464
Inventors:
John T. Yue - Los Altos CA
Shekhar Pramanick - Fremont CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 7166
G01N 2572
G01N 2720
US Classification:
437 8
Abstract:
Voids in a metallization pattern comprising a barrier layer, such as those generated by stress migration, are detected by applying a current across a test section of the metallization pattern to generate hot spots which are detected as by employing an infrared microscope or with a liquid crystalline material.

Double Density V Nonvolatile Memory Cell

US Patent:
5923063, Jul 13, 1999
Filed:
Feb 19, 1998
Appl. No.:
9/026358
Inventors:
Yowjuang W. Liu - San Jose CA
Donald L. Wollesen - Saratoga CA
John T. Yue - Los Altos CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2976
H01L 2988
H01L 29788
H01L 29792
US Classification:
257316
Abstract:
Floating gates of nonvolatile memory cells are formed in pairs within a pyramidal or truncated pyramidal opening in a semiconductor layer between a top surface thereof and a heavily doped source region spaced from the surface of the semiconductor layer. The floating gates control the conductance of channel regions formed along the sloped sidewalls of the pyramidal openings between surface drains and the buried source region.

Test Method For Predicting Hot-Carrier Induced Leakage Over Time In Short-Channel Igfets And Products Designed In Accordance With Test Results

US Patent:
5600578, Feb 4, 1997
Filed:
Aug 2, 1993
Appl. No.:
8/101251
Inventors:
Hao Fang - Cupertino CA
Peng Fang - Milpitas CA
John T. Yue - Los Altos CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 3126
G06F 1750
US Classification:
364578
Abstract:
A test method and apparatus are provided for predicting hot-carrier induced leakage over time in IGFET's. Test results are used to show how choice of channel length and stress voltages critically affect hot-carrier-induced leakage (HCIL) leakage over time, particularly in devices having submicron channel lengths. Models are developed for predicting leakage current over the long term given short term test results. Alternative design strategies are proposed for reliably satisfying long term leakage requirements.

Possible Relatives

Harry Yue  Helen W Yue  Henry Yue  James C Yue  Sarah P Yue  Yuan Yue  Albert Yue  John J Last  John J Stan  John C Stanaway 

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