Joseph P Ellul, Age 80Scottsdale, AZ

6358809, Mar 19, 2002

Jan 16, 2001

09/764812

Glenn Nobinger - Santa Clara CA
Alexander Kalnitsky - Portland OR
Melvin Schmidt - San Jose CA
Jonathan Herman - San Jose CA
Viktor Zekeriya - Palo Alto CA
Vijaykumar Ullal - Saratoga CA
Daniel H. Rosenblatt - San Carlos CA
Joseph P. Ellul - San Jose CA

Maxim Integrated Products, Inc. - Sunnyvale CA

H01L 2120

438382, 438238, 438385

A method of modifying a layer of thin film composite material to achieve one or more desired properties for the thin film layer which cannot be achieved by heat treatment at all practical temperatures of operation allowable by particular integrated circuit processes. In particular, the thin film composite material is subjected to an ion implantation process. Depending on the doping species, the doping concentration, the doping energy, and other ion implantation parameters, one or more properties of the deposited thin film resistive layer can be modified. Such properties may include electrical, optical, thermal and physical properties. For instance, the sheet resistance and/or the temperature coefficient of resistance of the thin film composite material may be increased or decreased by appropriately implanting ions into the material. The ion implantation can be applied globally in order to modify one or more properties of the entire deposited thin film composite layer. Alternatively, the ion implantation can be applied regionally in order to modify the thin film composite material at a first region, not modify the thin film composite material at a second region, and/or modify the thin film composite material in another way at a third region.

6475873, Nov 5, 2002

Aug 4, 2000

09/631581

Alexander Kalnitsky - Portland OR
Robert F. Scheer - Portland OR
Joseph P. Ellul - San Jose CA

Maxim Integrated Products, Inc. - Sunnyvale CA

H01L 2120

438384, 438382, 438385, 257359, 257379, 257516

A new and improved method of forming a thin film resistor is provided herein that overcomes many of the drawbacks of prior art methods. More specifically, the new method of forming a thin film provides for a well-controlled dielectric thickness under the thin film resistor which is useful for laser trimming purpose. The preferred thickness of the dielectric layer is an integer of a quarter wavelength of the optical energy used to laser trim the resistor. The new method also provides contacts to the thin film resistor that do not directly contact the thin film resistor so as to prevent any adverse process effects to the thin film resistor. More specifically, the method of forming a thin film resistor includes the steps of forming a pair of spaced-apart polysilicon islands over a semiconductor substrate, forming a dielectric layer over and between the polysilicon islands, forming contact holes through the dielectric layer to expose respective first regions of the polysilicon islands, forming a layer of thin film resistive material that extends between respective first regions of the polysilicon islands, forming another dielectric layer over the polysilicon islands and over the thin film resistive material layer, and forming metal contacts through the second dielectric layer in a manner that they make contact to respective second regions of the polysilicon islands, wherein the first and second regions of the polysilicon islands are different.

7943473, May 17, 2011

Jan 13, 2009

12/352679

Joseph Paul Ellul - San Jose CA, US
Khanh Tran - Milpitas CA, US
Albert Bergemont - Palo Alto CA, US

Maxim Integrated Products, Inc. - Sunnyvale CA

H01L 21/20

438386, 438381

Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.

8344478, Jan 1, 2013

Oct 23, 2009

12/605010

Joseph P. Ellul - San Jose CA, US
Khanh Tran - Milpitas CA, US
Edward Martin Godshalk - Newberg OR, US
Albert Bergemont - Palo Alto CA, US

Maxim Integrated Products, Inc. - San Jose CA

H01L 21/768
H01L 29/86

257531, 257585, 257E21585, 257E29325, 438622

Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

2007024, Oct 25, 2007

Apr 19, 2006

11/407441

Joseph Ellul - San Jose CA, US
Melvin Schmidt - San Jose CA, US
Viktor Zekeriya - Atherton CA, US
Rajiv Patel - San Jose CA, US
Jack Kelly - San Jose CA, US

C23C 14/00

204298020

Plasma systems with magnetic filter devices to alter film deposition/etching characteristics by altering the effective magnetic field distribution. The magnetic filter devices are placed between the magnet or magnets and a target, typically a semiconductor wafer, and selected and configured to alter the magnetic field to obtain the desired processing results. For deposition, the magnetic filter may be chosen to provide more uniform deposition, to provide increased deposition rates at or adjacent the edges of a wafer to compensate for increased etching rates at the edges of a wafer in a subsequent etching or polishing process. For annealing and doping, the magnetic field may be altered to provide more uniform equivalent annealing or doping across the wafer. Various applications are disclosed.

2008029, Dec 4, 2008

Aug 14, 2008

12/191505

Joseph Paul Ellul - San Jose CA, US
Melvin C. Schmidt - San Jose CA, US
Viktor Zekeriya - Atherton CA, US
Rajiv L. Patel - San Jose CA, US
Jack Kelly - San Jose CA, US

MAXIM INTEGRATED PRODUCTS, INC. - Sunnyvale CA

C23C 14/34
H05H 1/46

204156

Plasma systems with magnetic filter devices to alter film deposition/etching characteristics by altering the effective magnetic field distribution. The magnetic filter devices are placed between the magnet or magnets and a target, typically a semiconductor wafer, and selected and configured to alter the magnetic field to obtain the desired processing results. For deposition, the magnetic filter may be chosen to provide more uniform deposition, to provide increased deposition rates at or adjacent the edges of a wafer to compensate for increased etching rates at the edges of a wafer in a subsequent etching or polishing process. For annealing and doping, the magnetic field may be altered to provide more uniform equivalent annealing or doping across the wafer. Various applications are disclosed.

2013007, Mar 21, 2013

Nov 14, 2012

13/677061

Joseph P. Ellul - San Jose CA, US
Khanh Tran - Milpitas CA, US
Edward Martin Godshalk - Newberg OR, US
Albert Bergemont - Palo Alto CA, US

H01L 49/02

438381

Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

2013010, May 2, 2013

Oct 28, 2011

13/284116

Albert Bergemont - Palo Alto CA, US
Uppili Sridhar - Cupertino CA, US
Joseph Ellul - San Jose CA, US
Yi-Sheng Anthony Sun - San Jose CA, US
Elliott Simons - Southborough MA, US

Maxim Integrated Products, Inc. - Sunnyvale CA

H01L 23/58
H01L 21/50

257659, 438122, 257E23002, 257E21499

A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.