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Jun Tang20 Willow Tree Ln, Irvine, CA 92612

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Known as:
Jun J Tang Jun Tang Zhao Jun T Tang

Jun Tang Phones & Addresses

20 Willow Tree Ln, Irvine, CA 92612 (949) 653-0648 (949) 654-8345

9132 El Rito Dr, Villa Park, CA 92861

Orange, CA

Las Vegas, NV

Dallas, TX

Los Angeles, CA

20 Willow Tree Ln, Irvine, CA 92612

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Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Mentions for Jun Tang

Jun Tang resumes & CV records

Resumes

Jun Tang Photo 35

Marketing Director

Position:
Marketing Director at Sinogenomax Co.,Ltd & China Human Genome Center at Beijing
Location:
Beijing Suburb, China
Industry:
Biotechnology
Work:
Sinogenomax Co.,Ltd & China Human Genome Center at Beijing - Beijing, P.R.China since Jul 2011
Marketing Director UT Southwestern Medical Center at Dallas - Dallas/Fort Worth Area Oct 2008 - May 2011
Post Doctoral Fellow
Education:
Wuhan University 2001 - 2008
Ph.D, Biochemistry and Biophysics
Jun Tang Photo 36

Jun Tang

Jun Tang Photo 37

Jun Tang

Jun Tang Photo 38

Jun Tang

Jun Tang Photo 39

Jun Tang

Location:
United States
Jun Tang Photo 40

Manager At Hotstuff

Position:
Manager at hotstuff
Location:
United States
Industry:
Consumer Services
Work:
hotstuff
Manager

Publications & IP owners

Us Patents

Smart Interface For Payload Transfers In Networking Applications

US Patent:
6967920, Nov 22, 2005
Filed:
Jul 23, 2001
Appl. No.:
09/911338
Inventors:
Michael Seidl - Richardson TX, US
Jun Tang - Plano TX, US
Zhicheng Tang - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H04J003/14
US Classification:
370230, 370368
Abstract:
An apparatus and method for improving data transfers between a network and a network device is provided. The apparatus comprising a data input, a programmable counter adapted to counting the number of data packets received, an interrupt generator for signaling a microprocessor upon a signal from said programmable counter, a data processing block for examining the contents of data packets for an end-of-packet flag, and an output.

Interleaver Address Generation In Turbo Decoders For Mobile Multimedia Multicast System Communication Systems

US Patent:
8102791, Jan 24, 2012
Filed:
Jul 25, 2008
Appl. No.:
12/179599
Inventors:
Jun Tang - Lake Forest CA, US
Assignee:
Newport Media, Inc. - Lake Forest CA
International Classification:
H04J 11/00
US Classification:
370312
Abstract:
Address generation for interleaving in a wireless communication system includes at least one input generation module to generate at least one input signal. A first address generator module and a second address generator module generate a first output address for interleaving and a second output address for interleaving. A selector module selects an address for interleaving from the first and the second output address based on predetermined criteria. At least one input translation module is receives an input signal and translate the received input signal to generate a nominal input signal based on a value of the received input signal. An address generation module generates an address for interleaving based on the nominal input signal.

Multi-Chip Antenna Diversity Picture-In-Picture Architecture

US Patent:
8482675, Jul 9, 2013
Filed:
Sep 30, 2010
Appl. No.:
12/894789
Inventors:
James Carwana - Aliso Viejo CA, US
Jun Tang - Lake Forest CA, US
Philip Treigherman - Newport Beach CA, US
Chaoliang T. Chen - Irvine CA, US
Tracy Denk - Aliso Viejo CA, US
Assignee:
Newport Media, Inc. - Lake Forest CA
International Classification:
H04N 5/44
H04N 5/45
US Classification:
348725, 348565
Abstract:
A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Adsl Downloading With Priority Transmit Queue

US Patent:
2003007, Apr 17, 2003
Filed:
Sep 19, 2002
Appl. No.:
10/247226
Inventors:
Zhicheng Tang - Plano TX, US
Jun Tang - San Jose CA, US
International Classification:
G06F015/16
US Classification:
709/237000, 709/232000
Abstract:
An improved ADSL system and system for downloading and uploading data packets between a server and a client is provided by the client having a normal first-in-first-out queue for sending uploading data to said server and a separate priority first-in-first-out queue for sending acknowledgments back to said server to enable the server to send more download data. The client determines if the priority queue is empty and sends the data packets only when the priority queue is empty.

Method And Apparatus For Performing Dual Active Scan

US Patent:
2004009, May 13, 2004
Filed:
Nov 7, 2002
Appl. No.:
10/289672
Inventors:
Zhicheng Tang - Plano TX, US
Jun Tang - San Jose CA, US
International Classification:
G06F015/177
US Classification:
709/220000
Abstract:
A dual active scan technique () helps reduce the problem of losing a preferred Wireless Local Area Network (WLAN) in a congested environment, and also allows the communication device () to become aware of other WLANs that may be available for use by a communication device (). The dual active scan () performs an active scan with preferred SSID followed by an active scan with broadcasting SSID.

Interleaver Address Generation In Turbo Decoders For Mobile Multimedia Multicast Communication Systems

US Patent:
2012006, Mar 15, 2012
Filed:
Nov 21, 2011
Appl. No.:
13/300817
Inventors:
Jun Tang - Lake Forest CA, US
Assignee:
NEWPORT MEDIA, INC. - Lake Forest CA
International Classification:
H04W 4/06
US Classification:
370312
Abstract:
Address generation for interleaving in a wireless communication system includes at least one input generation module to generate at least one input signal. A first address generator module and a second address generator module generate a first output address for interleaving and a second output address for interleaving. A selector module selects an address for interleaving from the first and the second output address based on predetermined criteria. At least one input translation module is receives an input signal and translate the received input signal to generate a nominal input signal based on a value of the received input signal. An address generation module generates an address for interleaving based on the nominal input signal.

Multi-Chip Antenna Diversity Picture-In-Picture Architecture

US Patent:
2013027, Oct 17, 2013
Filed:
May 21, 2013
Appl. No.:
13/899311
Inventors:
James Carwana - Aliso Viejo CA, US
Jun Tang - Irvine CA, US
Philip Treigherman - Newport Beach CA, US
Chaoliang T. Chen - Tustin CA, US
Tracy Denk - Aliso Viejo CA, US
Assignee:
NEWPORT MEDIA, INC. - Lake Forest CA
International Classification:
H04N 5/45
US Classification:
348565
Abstract:
A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Computer Operating Process Allocating Tasks Between First And Second Processors At Run Time Based Upon Current Processor Load

US Patent:
6298370, Oct 2, 2001
Filed:
Apr 4, 1997
Appl. No.:
8/833152
Inventors:
Jun Tang - Richardson TX
John Ling Wing So - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 900
US Classification:
709102
Abstract:
A process of operating a computer system (100). The computer system (100) has a storage (HDD, 110) holding an operating system (OS) and an application program (APP. exe), a first processor (106) having an instruction set, and a second processor (1730) having a different instruction set. The process includes steps of 1) running (2424) at least some of the operating system (OS) on the first processor (106) so that the first processor (106) sets up for at least part of the application program at run time at least one second processor object (VSP OBJECT 1); and 2) concurrently running the second processor (3310) to access the second processor object (VSP OBJECT1) and thereby determine operations for the second processor (1730) to access second processor instructions for said part of the application program (APP. exe) and data to be processed according to said second processor instructions, and running (2436) the second processor (1730) to process the data according to said second processor instructions. Other processes, systems, devices and methods are also disclosed.

Possible Relatives

De P Tang  Dennis C Tang  Derek M Tang  Eric A Tang  Eva R Tang  Fei G Tang  Felix V Tang  Jun P Mendoza  Jun C Marquez  Jun D Martin 

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