Inventors:
Kavita Nair - Eden Prairie MN
Ramesh Harjani - Minneapolis MN
Assignee:
Regents of the University of Minnesota - Minneapolis MN
International Classification:
H03M 106
Abstract:
An analog to digital method and apparatus corrects non-linearity error and gain error in a multiple stage pipeline analog to digital converter over a plurality of clock cycles. Preferably, continuous correction, during each of the plurality of clock cycles, of at least portion of non-linearity error introduced by a digital to analog conversion is performed in a first stage of the multiple stage pipeline analog to digital converter with use of an averaging over time of a first stage digital residue signal provided by the remainder stages of the multiple stage pipeline analog to digital converter. Such correction is used to provide a non-linearity corrected digital signal. Correction, during each of the plurality of clock cycles, of at least a portion of a gain error introduced by one or more amplifiers in the multiple stage pipeline analog to digital converter is provided by averaging the non-linearity corrected digital signal over time.