Kelvin Scott Vartti, Age 6511893 Imperial Ave, Lino Lakes, MN 55038

6374332, Apr 16, 2002

Sep 30, 1999

09/409756

Donald W. Mackenthun - Fridley MN
Kelvin S. Vartti - Hugo MN

Unisys Corporation - Blue Bell PA

G06F 1300

711145, 711150, 711151

An improved directory-based, hierarchical memory system is disclosed that is capable of simultaneously processing multiple ownership requests initiated by a processor that is coupled to the memory. An ownership request is initiated on behalf of a processor to obtain an exclusive copy of memory data that may then be modified by the processor. In the data processing system of the preferred embodiment, multiple processors are each coupled to a respective cache memory. These cache memories are further coupled to a hierarchical memory structure including a main memory and one or more additional intermediate levels of cache memory. As is known in the art, copies of addressable portions of the main memory may reside in one or more of the cache memories within the hierarchical memory system. A memory directory records the location and status of each addressable portion of memory so that coherency may be maintained. Prior to updating an addressable portion of memory in a respectively coupled cache, a processor must acquire an exclusively âownedâ copy of the requested memory portion from the hierarchical memory.

6625698, Sep 23, 2003

Dec 28, 2000

09/750637

Kelvin S. Vartti - Hugo MN

Unisys Corporation - Blue Bell PA

G06F 1200

711141, 711151, 711158

A system and method for controlling storage locks based on cache line ownership. Ownership of target data segments is acquired at a memory targeted by a first requesting device. A storage lock is enabled that prohibits requesting devices, other than the first requesting device, from acting on the target data segments during the time the targeted memory possesses ownership of the target data segments. A storage lock release signal is issued from the first requesting device to the targeted memory when exclusivity of the target data segments is no longer required at the first requesting device. In response, the storage lock at the targeted memory is released, thereby allowing other requesting devices to act on the target data segments.

6697925, Feb 24, 2004

Dec 22, 2000

09/748535

James L. Federici - Lino Lakes MN
Kelvin S. Vartti - Hugo MN
Robert M. Malek - White Bear Township MN
Lewis A. Boone - Fridley MN

Unisys Corporation - Blue Bell PA

G06F 1200

711167, 711122, 711141, 711154, 709248, 713400

A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the systems level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the multiple instruction processors within the data processing system thereby decreasing access time and user queuing. These individual dayclocks are each incremented at one microsecond intervals. However, these individual dayclocks require periodic synchronization to avoid system level time-tagging problems. This synchronization occurs at 20 microsecond intervals using the cache coherency maintenance hardware of the system.

6728835, Apr 27, 2004

Aug 30, 2000

09/650730

Mitchell A. Bauman - Circle Pines MN
Conrad S. Shimada - Oakdale MN
Kelvin S. Vartti - Hugo MN
William L. Borgerding - Minneapolis MN

Unisys Corporation - Blue Bell PA

G06F 1200

711122, 711133, 711135, 711136

An apparatus for and method of improving the efficiency of a level two cache memory. In response to a level one cache miss, a request is made to the level two cache. A signal sent with the request identifies when the requester does not anticipate a near term subsequent use for the requested data element. If a level two cache hit occurs, the requested data element is marked as least recently used in response to the signal. If a level two cache miss occurs, a request is made to level three storage. When the level three storage request is honored, the requested data element is immediately flushed from the level two cache memory in response to the signal.

6799249, Sep 28, 2004

Aug 30, 2000

09/651598

Donald C. Englin - Shoreview MN
Kelvin S. Vartti - Hugo MN

Unisys Corporation - Blue Bell PA

G06F 1200

711125, 711122, 711133

An apparatus for and method of queuing memory access requests resulting from level two cache memory misses. The requests are preferably queued separately by processor. To provide the most recent data to the system, write (i. e. , input) requests are optimally given preference over read (i. e. , output) requests for input/output processors. However, instruction processor program instruction fetches (i. e. , read-only requests) are preferably given priority over operand transfers (i. e. , read/write requests) to reduce instruction processor latency.

6816952, Nov 9, 2004

May 31, 2002

10/160947

Kelvin S. Vartti - Hugo MN
Wayne D. Ward - New Brighton MN
Hans C. Mikkelsen - Afton MN

Unisys Corporation - Blue Bell PA

G06F 1214

711163

The current invention provides an improved system and method for locking shared resources. The invention may operate in a data processing environment including a main memory system coupled to multiple instruction processors (IPs). Lock-type instructions are included within the hardware instruction set of ones of the IPs. These lock-type instructions are executed to gain access to a software-lock stored at a predetermined location within the main memory. After activating the software-lock, further, indivisible execution of the lock-type instruction causes one or more addresses associated with the software-lock to be retrieved. These addresses are used as pointers to, in turn, retrieve the data signals protected by the software-lock. Requests for the protected data signals are issued automatically by the hardware on behalf of the requesting IP, and the IP is allowed to continue instruction execution.

6857049, Feb 15, 2005

Aug 30, 2000

09/651488

Donald C. Englin - Shoreview MN, US
Kelvin S. Vartti - Hugo MN, US
James L. Federici - Lino Lakes MN, US

Unisys Corporation - Blue Bell PA

G06F012/00

711135, 711122, 711142, 711143

A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from managing the process of flushing old data from the second level cache memory. In the present invention, the second level cache memory is a store-in memory. Therefore, when data is to be deleted from the second level cache memory, a determination is made whether the data has been modified by the processor. If the data has been modified, the data must be rewritten to lower level memory. To free the second level cache memory for storage of the newly requested data, the data to be flush is loaded into a flush buffer for storage during the rewriting process.

6928517, Aug 9, 2005

Aug 30, 2000

09/651597

Donald C. Englin - Shoreview MN, US
Donald W. Mackenthun - Fridley MN, US
Kelvin S. Vartti - Hugo MN, US

Unisys Corporation - Blue Bell PA

G06F013/00

711122, 711146, 711151, 710 40

A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from enhancing the response to SNOOP requests. To accomplish this, the system memory bus is provided separate and independent paths to the level two cache and tag memories. Therefore, SNOOP requests are permitted to directly access the tag memories without reference to the cache memory. Secondly, the SNOOP requests are given a higher priority than operations associated with local processor data requests. Though this may slow down the local processor, the remote processors have less wait time for SNOOP operations improving overall system performance.