Kenneth Y Yun, Age 62Newport Coast, CA

Kenneth Yun Phones & Addresses

Newport Coast, CA

1662 Gascony Rd, Encinitas, CA 92024 (760) 452-6398

Campbell, CA

4221 Camino Sandoval, San Diego, CA 92130 (858) 794-9550

New York, NY

Orange, CA

Education

School / High School: Duke University School of Law

Ranks

Licence: New York - Currently registered Date: 1989

Mentions for Kenneth Y Yun

Professional Records

Lawyers & Attorneys

Kenneth Yun Photo 1

Kenneth Young-Gak Yun - Lawyer

Address:
Samjong Kpmg 10 Th Fl. Star Tower
(221) 120-010x (Office)
Licenses:
New York - Currently registered 1989
Education:
Duke University School of Law

Medicine Doctors

Kenneth S. Yun

Specialties:
Urology
Work:
Kaiser Permanente Medical Group
2045 N Franklin St, Denver, CO 80205
(303) 338-4545 (phone) (303) 861-3234 (fax)
Site
Education:
Medical School
Saint Louis University School of Medicine
Graduated: 2004
Procedures:
Thoracoscopy, Bladder Repair, Circumcision, Cystoscopy, Cystourethroscopy, Kidney Stone Lithotripsy, Nephrectomy, Prostate Biopsy, Transurethral Resection of Prostate, Urinary Flow Tests, Vaginal Repair, Vasectomy
Conditions:
Benign Prostatic Hypertrophy, Bladder Cancer, Calculus of the Urinary System, Erectile Dysfunction (ED), Inguinal Hernia, Kidney Cancer, Male Infertility, Prostate Cancer, Prostatitis, Testicular Cancer, Urinary Incontinence, Urinary Tract Infection (UT)
Languages:
English
Description:
Dr. Yun graduated from the Saint Louis University School of Medicine in 2004. He works in Denver, CO and specializes in Urology. Dr. Yun is affiliated with St Joseph Hospital.
Kenneth Yun Photo 2

Kenneth S Yun

Specialties:
Urology
General Practice
Education:
Saint Louis University (2004)

Resumes

Resumes

Kenneth Yun Photo 3

Kenneth Yun

Location:
Greater San Diego Area
Industry:
Higher Education
Kenneth Yun Photo 4

Kenneth Yun

Location:
United States
Kenneth Yun Photo 5

Kenneth Yun

Location:
United States

Business Records

Name / TitleCompany / ClassificationPhones & Addresses
Kenneth Yun
Mbr
Yuni Systems, LLC 1662 Gascony Rd, Encinitas, CA 92024

Publications

Us Patents

Earliest-Deadline-First Queuing Cell Switching Architecture And Method

US Patent:
6791992, Sep 14, 2004
Filed:
Jun 5, 2000
Appl. No.:
09/586812
Inventors:
Kenneth Y. Yun - San Diego CA
Kevin W. James - San Diego CA
Assignee:
The Regents of the University of California - LaJolla CA
International Classification:
H04L 1228
US Classification:
370415, 370461, 370462
Abstract:
The cell switching architecture of the present invention uses at least one earliest deadline first (EDF) queue for each of the output ports in a cell switch so that no two output ports have a common earliest-deadline-first queue. Cells are arranged in each EDF queue according to deadline, but each EDF queue only contains cells for a single destination output port. Each input port also has an input queue with an EDF queue for each of the output ports, and each EDF queue arranges the cells for a single output port. Many equivalent cells may be represented by a single EDF queue entry, enabling large buffer capacity to be supported by small EDF queues. The architecture provides a method for switching cells between a plurality of input ports and a plurality of output ports. Cells are accepted from input ports into a plurality of corresponding input queues. Cells are sorted into groups according to the destination output port such that each group includes cells destined for a single output port.

System And Method For Tolerating Data Link Faults In A Packet Communications Switch Fabric

US Patent:
7352694, Apr 1, 2008
Filed:
Feb 24, 2003
Appl. No.:
10/373139
Inventors:
Philip Michael Clovis - San Diego CA,
Eli James Aubrey Fernald - San Diego CA,
John David Huber - San Diego CA,
Kirk Alvin Miller - San Diego CA,
Sushil Kumar Singh - San Diego CA,
Prayag Bhanubhai Patel - San Diego CA,
Kenneth Yi Yun - San Diego CA,
George Beshara Bendak - San Diego CA,
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G01R 31/08
G06F 11/00
US Classification:
370217, 370225
Abstract:
A system and method are provided for tolerating data line faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of ingress port card ports, the plurality of information packets addressing a plurality of egress port card ports; selectively connecting port card ports to port card backplane data links; selectively connecting port card backplane data links and crossbars; sensing a connection fault in a backplane data link; in response to sensing the fault, reselecting connections between the port card ports and the port card backplane data links; in response to reselecting connections between the port card ports and the port card backplane data links, serially transferring packets through the port cards; serially transferring packets through the crossbars to the egress port cards; and, suspending use of the faulty connection.

Apparatus And Method For Self-Timed Marking Of Variable Length Instructions Having Length-Affecting Prefix Bytes

US Patent:
5948096, Sep 7, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/997462
Inventors:
Ran Ginosar - Nofit,
Rakefet Kol - Haifa,
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712210
Abstract:
A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

Efficient Self-Timed Marking Of Lengthy Variable Length Instructions

US Patent:
5941982, Aug 24, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/997461
Inventors:
Ran Ginosar - Nofit,
Rakefet Kol - Haifa,
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712210
Abstract:
A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

Apparatus And Method For Parallel Processing And Self-Timed Serial Marking Of Variable Length Instructions

US Patent:
5978899, Nov 2, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/997457
Inventors:
Ran Ginosar - Nofit,
Rakefet Kol - Haifa,
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712210
Abstract:
Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

Spread-Spectrum Receiver And Reception Method

US Patent:
8208513, Jun 26, 2012
Filed:
Mar 30, 2007
Appl. No.:
12/294543
Inventors:
Manish Amde - La Jolla CA,
Rene L. Cruz - San Diego CA,
Kenneth Yun - San Diego CA,
Assignee:
The Regents of the University of California - Oakland CA
International Classification:
H04B 1/00
US Classification:
375147, 375140, 375130, 375 E1002
Abstract:
Receivers and reception methods conduct spread spectrum reception using the energy of multiple bits, preferably a substantial number of bits, in a packet for correct alignment of the spreading code at the receiver. Code acquisition, as well as packet detection and acquisition are provided by embodiments of the invention. Preferred embodiment receivers and reception methods provide packet detection at low SINR looking at energy of multiple bits of the packet, frame synchronization using short preamble, timing recovery at low SINR looking at energy of multiple bits of the packet, quick code acquisition using parallel search for all possible code phases, code acquisition at low SINR, and tracking of acquired timing and code phase. Preferred embodiment receivers and reception methods use the energy of multiple bits for making decisions.

Switch Fabric Backplane Flow Management Using Credit-Based Flow Control

US Patent:
7263066, Aug 28, 2007
Filed:
Mar 24, 2003
Appl. No.:
10/395369
Inventors:
Kenneth Yi Yun - San Diego CA,
Jianfeng Shi - Encinitas CA,
Viet Linh Do - La Jolla CA,
Michael John Hellmer - Carlsbad CA,
Kevin Warren James - San Diego CA,
Kirk Alvin Miller - San Diego CA,
Sushil Kumar Singh - San Diego CA,
David Thomas Dougherty - Rancho Santa Fe CA,
John Calvin Leung - San Diego CA,
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H04L 12/26
US Classification:
370236, 370392, 370412, 370429
Abstract:
A credit-based system and method are provided for managing backplane traffic flow in a packet communications switch fabric. The method comprises: accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between an input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; and, using modified destination information, sending the generated credits to increment the counter. In some aspects, modifying the destination information in the received packet headers includes: extracting the output port card termination from the card field; and, inserting the input port card source in the card field.

System And Method For Reevaluating Granted Arbitrated Bids

US Patent:
7889729, Feb 15, 2011
Filed:
Apr 14, 2008
Appl. No.:
12/102415
Inventors:
Kenneth Yi Yun - San Diego CA,
Kevin Warren James - San Diego CA,
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H04L 12/28
US Classification:
370389, 370351
Abstract:
A system and method are provided for fairly distributing grants for access to switch outputs, through crossbars, between switch input channels. Crossbars are granted access between specified switch inputs and switch outputs, and the least recently used input channels are associated with selected switch outputs. A history of the previous channel transaction is maintained for each switch output, and channels are nominated in a rotation through a priority channel list. The present invention bid grant algorithm permits information packets to be transferred across a switch in the time between a bid submission and a bid grant.

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