Kenneth Y Yun, Age 651662 Gascony Rd, Encinitas, CA 92024

6791992, Sep 14, 2004

Jun 5, 2000

09/586812

Kenneth Y. Yun - San Diego CA
Kevin W. James - San Diego CA

The Regents of the University of California - LaJolla CA

H04L 1228

370415, 370461, 370462

The cell switching architecture of the present invention uses at least one earliest deadline first (EDF) queue for each of the output ports in a cell switch so that no two output ports have a common earliest-deadline-first queue. Cells are arranged in each EDF queue according to deadline, but each EDF queue only contains cells for a single destination output port. Each input port also has an input queue with an EDF queue for each of the output ports, and each EDF queue arranges the cells for a single output port. Many equivalent cells may be represented by a single EDF queue entry, enabling large buffer capacity to be supported by small EDF queues. The architecture provides a method for switching cells between a plurality of input ports and a plurality of output ports. Cells are accepted from input ports into a plurality of corresponding input queues. Cells are sorted into groups according to the destination output port such that each group includes cells destined for a single output port.

7352694, Apr 1, 2008

Feb 24, 2003

10/373139

Philip Michael Clovis - San Diego CA,
Eli James Aubrey Fernald - San Diego CA,
John David Huber - San Diego CA,
Kirk Alvin Miller - San Diego CA,
Sushil Kumar Singh - San Diego CA,
Prayag Bhanubhai Patel - San Diego CA,
Kenneth Yi Yun - San Diego CA,
George Beshara Bendak - San Diego CA,

Applied Micro Circuits Corporation - San Diego CA

G01R 31/08
G06F 11/00

370217, 370225

A system and method are provided for tolerating data line faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of ingress port card ports, the plurality of information packets addressing a plurality of egress port card ports; selectively connecting port card ports to port card backplane data links; selectively connecting port card backplane data links and crossbars; sensing a connection fault in a backplane data link; in response to sensing the fault, reselecting connections between the port card ports and the port card backplane data links; in response to reselecting connections between the port card ports and the port card backplane data links, serially transferring packets through the port cards; serially transferring packets through the crossbars to the egress port cards; and, suspending use of the faulty connection.

5948096, Sep 7, 1999

Dec 23, 1997

8/997462

Ran Ginosar - Nofit,
Rakefet Kol - Haifa,
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 930

712210

A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

5941982, Aug 24, 1999

Dec 23, 1997

8/997461

Ran Ginosar - Nofit,
Rakefet Kol - Haifa,
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 930

712210

A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

5978899, Nov 2, 1999

Dec 23, 1997

8/997457

Ran Ginosar - Nofit,
Rakefet Kol - Haifa,
Kenneth Scott Stevens - Hillsboro OR
Peter A. Beerel - Long Beach CA
Kenneth Yi Yun - San Diego CA
Christopher John Myers - Salt Lake City UT
Shai Rotem - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 930

712210

Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

8208513, Jun 26, 2012

Mar 30, 2007

12/294543

Manish Amde - La Jolla CA,
Rene L. Cruz - San Diego CA,
Kenneth Yun - San Diego CA,

The Regents of the University of California - Oakland CA

H04B 1/00

375147, 375140, 375130, 375 E1002

Receivers and reception methods conduct spread spectrum reception using the energy of multiple bits, preferably a substantial number of bits, in a packet for correct alignment of the spreading code at the receiver. Code acquisition, as well as packet detection and acquisition are provided by embodiments of the invention. Preferred embodiment receivers and reception methods provide packet detection at low SINR looking at energy of multiple bits of the packet, frame synchronization using short preamble, timing recovery at low SINR looking at energy of multiple bits of the packet, quick code acquisition using parallel search for all possible code phases, code acquisition at low SINR, and tracking of acquired timing and code phase. Preferred embodiment receivers and reception methods use the energy of multiple bits for making decisions.

7263066, Aug 28, 2007

Mar 24, 2003

10/395369

Kenneth Yi Yun - San Diego CA,
Jianfeng Shi - Encinitas CA,
Viet Linh Do - La Jolla CA,
Michael John Hellmer - Carlsbad CA,
Kevin Warren James - San Diego CA,
Kirk Alvin Miller - San Diego CA,
Sushil Kumar Singh - San Diego CA,
David Thomas Dougherty - Rancho Santa Fe CA,
John Calvin Leung - San Diego CA,

Applied Micro Circuits Corporation - San Diego CA

H04L 12/26

370236, 370392, 370412, 370429

A credit-based system and method are provided for managing backplane traffic flow in a packet communications switch fabric. The method comprises: accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between an input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; and, using modified destination information, sending the generated credits to increment the counter. In some aspects, modifying the destination information in the received packet headers includes: extracting the output port card termination from the card field; and, inserting the input port card source in the card field.

7889729, Feb 15, 2011

Apr 14, 2008

12/102415

Kenneth Yi Yun - San Diego CA,
Kevin Warren James - San Diego CA,

Qualcomm Incorporated - San Diego CA

H04L 12/28

370389, 370351

A system and method are provided for fairly distributing grants for access to switch outputs, through crossbars, between switch input channels. Crossbars are granted access between specified switch inputs and switch outputs, and the least recently used input channels are associated with selected switch outputs. A history of the previous channel transaction is maintained for each switch output, and channels are nominated in a rotation through a priority channel list. The present invention bid grant algorithm permits information packets to be transferred across a switch in the time between a bid submission and a bid grant.