Kenny W Ngan, Age 64Davis, CA

6372301, Apr 16, 2002

Dec 22, 1998

09/218703

Murali Narasimhan - San Jose CA
Vikram Pavate - San Jose CA
Kenny King-Tai Ngan - Fremont CA
Xiangbing Li - San Jose CA

Applied Materials, Inc. - Santa Clara CA

C23C 1402

427534, 427535, 427250, 427255391, 427255394, 2041921

The present invention generally provides a method for stabilizing a halogen-doped silicon oxide film, particularly a fluorinated silicon oxide film. The invention also provides a method for preventing loosely bonded halogen atoms from reacting with components of the barrier layer during subsequent processing of the substrate. The invention provides a hydrogen plasma treatment of the halogen-doped silicon oxide film without subjecting the substrate to a heated environment that may damage the substrate and the structures formed on the substrate. The invention also improves the adhesion strength between the halogen-doped silicon oxide film and the barrier layer. Furthermore, the hydrogen plasma treatment can be practiced in a variety of plasma processing chambers of an integrated process sequence, including pre-clean chambers, physical vapor deposition chambers, chemical vapor deposition chambers, etch chambers and other plasma processing chambers.

6420260, Jul 16, 2002

Oct 24, 2000

09/695941

Kenny King-tai Ngan - Fremont CA
Seshadri Ramaswami - San Jose CA

Applied Materials, Inc. - Santa Clara CA

H01L 214763

438627, 438628, 438648, 438653, 438654, 438685, 438688

The present disclosure pertains to particular Ti/TiN/TiN barrier/wetting layer structures which enable the warm aluminum filling of high aspect vias while providing an aluminum fill exhibiting a high degree of aluminum 111 crystal orientation. It has been discovered that an improved Ti/TiN/TiN barrier layer deposited using IMP techniques can be obtained by increasing the thickness of the first layer of Ti to range from greater than about 100 to about 500 (the feature geometry controls the upper thickness limit); by decreasing the thickness of the TiN second layer to range from greater than about 100 to less than about 800 (preferably less than about 600 ); and, by controlling the application of the TiN third layer to provide a Ti content ranging from about 50 atomic percent titanium (stoichiometric) to about 100 atomic percent titanium. Preferably the TiN third layer is formed at the end of the deposition of the TiN second layer and exhibits a Ti content gradient which begins at a stoichiometric, 50 atomic percent, Ti content and ends at a Ti content of about 100 atomic percent. The thickness of the TiN third layer preferably ranges from about 15 to about 500.

6426282, Jul 30, 2002

May 4, 2000

09/565569

Dinesh Saigal - San Jose CA
Shankarram Athreya - Sunnyvale CA
Kenny King-Tai Ngan - Fremont CA
Lisa L. Yang - San Jose CA

Applied Materials, Inc. - Santa Clara CA

H01L 2144

438613, 438653

A method of forming solder bumps on a semiconductor wafer utilizing a low temperature biasable electrostatic chuck. In particular, the method comprises the steps of providing at least one bond pad on the semiconductor wafer, forming a barrier layer over the bond pad, and forming the solder bumps upon the at least one bond pad. By controlling the temperature and biasing of the electrostatic chuck, the barrier layer, such as nickel vanadium, exhibits a low tensile or compressive stress.

6625003, Sep 23, 2003

Nov 1, 2002

10/286688

David Loo - San Jose CA
Kenny K. Ngan - Fremont CA
Bradley O. Stimson - San Jose CA

Applied Materials, Inc. - Santa Clara CA

H01G 300

361234, 361233

A bipolar electrostatic chuck containing apparatus, and a concomitant method, for balancing an electrostatic force that the bipolar electrostatic chuck imparts upon a workpiece. More specifically, the bipolar electrostatic chuck contains a chuck body having a pair of electrodes embedded therein, a primary power supply and an offset power supply. Each electrode within the bipolar electrostatic chuck is respectively connected to a terminal on the primary power. Based upon a voltage produced by the primary power supply and a bias voltage of the workpiece, an offset voltage is applied by the offset power supply to one of the terminals, thus balancing the electrostatic force applied to the workpiece.

6672864, Jan 6, 2004

Aug 27, 2002

10/229879

Hougong Wang - Pleasanton CA
Zheng Xu - Santa Cruz CA
Kenny King-Tai Ngan - Fremont CA

Applied Materials, Inc. - Santa Clara CA

F27D 316

432 5, 432171, 432243, 414217, 414804

A positive pressure gradient is maintained across an open access port of an interface chamber such as a load lock chamber which provides an interface between a low pressure chamber such as a transfer or buffer chamber, and a high pressure area such as a staging area or factory interface area. When the access port of the interface chamber is open to the high-pressure area, the positive pressure gradient may be used in some applications to inhibit the flow of gasses from the high-pressure area into the interior of the interface chamber.

6899799, May 31, 2005

Oct 2, 2002

10/263167

Kenny King-Tai Ngan - Fremont CA, US
Ying Yin Hui - Fremont CA, US
Seshadri Ramaswami - San Jose CA, US

Applied Materials, Inc. - Santa Clara CA

C23C014/35

20429825, 20429803, 20429806

Increased sidewall coverage by a sputtered material is achieved by generating an ionizing plasma in a relatively low pressure sputtering gas. By reducing the pressure of the sputtering gas, it is believed that the ionization rate of the deposition material passing through the plasma is correspondingly reduced which in turn is believed to increase the sidewall coverage by the underlayer. Although the ionization rate is decreased, sufficient bottom coverage of the by the material is maintained. In an alternative embodiment, increased sidewall coverage by the material may be achieved even in a high density plasma chamber by generating the high density plasma only during an initial portion of the material deposition. Once good bottom coverage has been achieved, the RF power to the coil generating the high density plasma may be turned off entirely and the remainder of the deposition conducted without the high density plasma. Consequently, it has been found that good sidewall coverage is achieved in the latter part of the deposition.

6945857, Sep 20, 2005

Jul 8, 2004

10/888941

Trung Doan - Los Gatos CA, US
Venkata R. Balagani - Gilroy CA, US
Kenny King-Tai Ngan - Fremont CA, US

Applied Materials, Inc. - Santa Clara CA

B24B001/00

451 56, 451 72, 451443, 451539

A recycled polishing pad conditioner comprises a base plate and a reversed abrasive disc that is flipped over from its original configuration. The reversed disc comprises an exposed abrasive face having an unused abrasive face comprising abrasive particles. A bond face of the disc is affixed to the base plate, the bond face comprising a used abrasive face that was previously used to condition polishing pads. Also described is a pad conditioner having an abrasive face comprising exposed portions of abrasive particles, with at least about 60% of the abrasive particles having a crystalline structure with substantially the same crystal symmetry.

7006888, Feb 28, 2006

Jan 14, 2002

10/046954

Hougong Wang - Pleasanton CA, US
Kenny King-Tai Ngan - Fremont CA, US
Zheng Xu - Foster City CA, US

Applied Materials, Inc. - Santa Clara CA

G06F 19/00

700121, 700 96, 29 2501, 414217

Embodiments of the present invention provide a method, article of manufacture, and apparatus for processing semiconductor wafers. The method includes preheating a semiconductor wafer in two types of chambers. In one embodiment, a first preheating chamber is a load lock and a second preheating chamber is a transition chamber. Semiconductor wafer processing systems which can perform embodiments of the method are presented.