Kevin Bruc Normoyle, Age 482642 Van Ness Ave APT 105, San Francisco, CA 94109

6446168, Sep 3, 2002

Mar 22, 2000

09/532995

Kevin Normoyle - Santa Clara CA
Bruce E. Petrick - Sunnyvale CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1200

711128, 711118

A method of dynamically switching mapping schemes for cache includes a microprocessor, a first mapping scheme, a second mapping scheme and switching circuitry for switching between the first mapping scheme and the second mapping scheme. The microprocessor is in communication with the cache through the switching circuitry and stores information within the cache using one of the first mapping scheme and second mapping scheme. Also, monitoring circuitry for determining whether one of instructions and load/store operations is using the cache is included. Further, the switching circuitry switches between the first mapping scheme and the second mapping scheme based on which one of instructions and load/store operations is using the cache.

6477622, Nov 5, 2002

Sep 26, 2000

09/670856

Kevin B. Normoyle - Santa Clara CA
Meera Kasinathan - Sunnyvale CA
Rajasekhar Cherabuddi - Cupertino CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1200

711143, 711141, 711146

The main cache of a processor in a multiprocessor computing system is coupled to receive writeback data during writeback operations. In one embodiment, during writeback operations, e. g. , for a cache miss, dirty data in the main cache is merged with modified data from an associated write cache, and the resultant writeback data line is loaded into a writeback buffer. The writeback data is also written back into the main cache, and is maintained in the main cache until replaced by new data. Subsequent requests (i. e. , snoops) for the data are then serviced from the main cache, rather than from the writeback buffer. In some embodiments, further modifications of the writeback data in the main cache are prevented. The writeback data line in the main cache remains valid until read data for the cache miss is returned, thereby ensuring that the read address reaches the system interface for proper bus ordering before the writeback line is lost. In one embodiment, the writeback operation is paired with the read operation for the cache miss to ensure that upon completion of the read operation, the writeback address has reached the system interface for bus ordering, thereby maintaining cache coherency while allowing requests to be serviced from the main cache.

6496917, Dec 17, 2002

Feb 7, 2000

09/499264

Rajasekhar Cherabuddi - Cupertino CA
Kevin B. Normoyle - Santa Clara CA
Brian J. McGee - San Jose CA
Meera Kasinathan - Sunnyvale CA
Anup Sharma - Santa Clara CA
Sutikshan Bhutani - Sunnyvale CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1200

711204, 711120, 711167, 711169

A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative. If, on the other hand, the subsequent transaction requesting the specified data is a write transaction, the speculative request is canceled.

6535966, Mar 18, 2003

May 17, 2000

09/572646

Rajasekhar Cherabuddi - Cupertino CA
Kevin Normoyle - Santa Clara CA
Brian McGee - San Jose CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1200

711154, 711108, 711 5, 36523003, 36523008

A memory controller for a memory subsystem of a computer system connects to a processor bus. The memory controller is for use with memory devices such as RDRAM or DDR SDRAM that allow for multiple open pages. Memory references are remapped by an address mapper and processed by a page tracking buffer to keep track of open pages in the memory devices. The controller also has a state machine, and an interface to memory devices. The page tracking buffer has a row address content addressable memory for determining when a reference is in an open page, and a bank content addressable memory for determining when a reference is to the same bank as an open page. The controller closes open pages of a bank prior to opening new pages in that bank. The page tracking buffer has fewer lines than the product of the maximum number of memory devices times the maximum number of simultaneously open pages of each device, but provides for tracking any page of any of the memory devices.

6553435, Apr 22, 2003

Jan 12, 1999

09/229013

Kevin B. Normoyle - Santa Clara CA
Michael A. Csoppenszky - Los Gatos CA
Jaybharat Boddu - Santa Clara CA
Jui-Cheng Su - Sunnyvale CA
Alex S. Han - San Jose CA
Rajasekhar Cherabuddi - Sunnyvale CA
Tzungren Tzeng - San Jose CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1328

710 22, 710 36, 710 38, 711100

A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.

6900674, May 31, 2005

Feb 27, 2003

10/375587

Massimo Sutera - Sunnyvale CA, US
Daniel Y. Cheung - Cupertino CA, US
Lan Lee - Palo Alto CA, US
Kevin B. Normoyle - Santa Clara CA, US
Sung-Hun Oh - Sunnyvale CA, US
Ivana Capellano - Palermo, IT

Sun Microsystems, Inc. - Santa Clara CA

H03L007/00

327144, 327160

In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

7143304, Nov 28, 2006

May 30, 2003

10/452678

Sharath Raghava - San Jose CA, US
Kevin Normoyle - Santa Clara CA, US
Christopher Furman - Gilroy CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 1/12

713600, 713400, 713503

An apparatus for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk is supplied by the same PLL that provides the main clock signal lg_clk. According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.

7203890, Apr 10, 2007

Jun 16, 2004

10/710066

Kevin B. Normoyle - Santa Clara CA, US

Azul Systems, Inc. - Mountain View CA

G11C 29/52
G11C 29/42

714768, 714763, 714766

A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4 bits or less. Rather than generating address parity, which is poor at detecting even numbers of errors, a cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to just 4 address check bits using the CRC code. The 4 address check bits are merged (XOR'ed) with two 4-bit nibbles of the data SbEC/DbED code to generate a merged ECC codeword that is stored in memory. An address error causes a 2-nibble mis-match due to the redundant merging of the 4 address check bits with 2 nibbles of data correction code. The CRC code is ideal for detecting even numbers of errors common with multiplexed-address DRAMs.