Kin L Cheung, Age 50Flushing, NY

6365426, Apr 2, 2002

Apr 30, 2000

09/560935

Kin P. Cheung - Hoboken NJ
Philip W. Mason - Kissimmee FL

Agere Systems Guardian Corporation - Orlando FL

H01L 2166

438 17, 438199, 324769

The present invention provides a method of determining a reliability of a semiconductor device. In an exemplary embodiment, the method determines an oxide stress voltage as a function of an antenna ratio of a semiconductor device, determines an oxide area of the semiconductor device and determines a failure fraction of the semiconductor device as a function of the oxide stress voltage and the oxide area.

6469390, Oct 22, 2002

Apr 21, 1999

09/296001

Kin Ping Cheung - Hoboken NJ
Chien-Shing Pai - Bridgewater NJ
Wei Zhu - Warren NJ

Agere Systems Guardian Corp. - Orlando FL

H01L 2348

257758, 257752, 257759, 257642, 257637

It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i. e. , the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e. g. , shallow trench isolation), an active device structure (e. g. , a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3. 5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

6524872, Feb 25, 2003

May 24, 1999

09/317430

Kin P. Cheung - Hoboken NJ

Agere Systems Inc. - Berkeley Heights NJ

H01L 2166

438 17, 438 10, 438 14

The invention relates to the measurement and monitoring of plasma-damage, and to the evaluation of the lifetime of integrated circuits under nominal operating conditions. The method calculates the intrinsic, or damage-free, lifetime of a particular transistor device by measuring the change in transconductance as a function of time for a given device over a short period of time. The change in the transconductance as a function of time, i. e. , the slope of the degradation curve, is measured and then compared to a reference value. The present invention thus allows the use of hot-carrier stress method to determine plasma damage in a time efficient manner without the need of applying high acceleration voltages.

6936494, Aug 30, 2005

Oct 22, 2003

10/691029

Kin P. Cheung - Hoboken NJ, US

Rutgers, The State University of New Jersey - New Brunswick NJ

H01L021/00

438 55, 438 51, 438125, 438126

A process for hermetically packaging a microscopic structure including a MEMS device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material patterned by lithography over the capping layer, providing a plurality of vias through the support layer by lithography, removing the capping layer via wet etching to leave the support layer intact in the form of a shell having a cavity occupied by the microscopic structure, depositing a metal layer over the capping layer that is thick enough to provide a barrier against gas permeation, but thin enough to leave the vias open, and selectively applying under high vacuum a laser beam to the metal proximate each via for a sufficient period of time to melt the metal for sealing the via.

7548067, Jun 16, 2009

Oct 25, 2006

11/552779

Kin P. Cheung - Hoboken NJ, US
Dawei Heh - Austin TX, US
Byoung Hun Lee - Austin TX, US
Rino Choi - Austin TX, US

Sematech, Inc. - Austin TX
Rutgers University - New Brunswick NJ

G01R 31/11
G01R 27/04
G01R 27/32
G01R 31/26

324533, 324534, 324642, 324769

Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.

2005018, Sep 1, 2005

May 3, 2005

11/120704

Kin Cheung - Hoboken NJ, US

H01L029/06

257619000, 257704000, 257659000, 257660000

A process for hermetically packaging a microscopic structure including a MEMS device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material patterned by lithography over the capping layer, providing a plurality of vias through the support layer by lithography, removing the capping layer via wet etching to leave the support layer intact in the form of a shell having a cavity occupied by the microscopic structure, depositing a metal layer over the capping layer that is thick enough to provide a barrier against gas permeation, but thin enough to leave the vias open, and selectively applying under high vacuum a laser beam to the metal proximate each via for a sufficient period of time to melt the metal for sealing the via.

2005025, Nov 10, 2005

Jun 14, 2005

11/152429

Kin Cheung - Hoboken NJ, US

H01L021/48

438125000

A process for packaging and sealing a microscopic structure device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material patterned by lithography over the capping layer, providing a plurality of vias through the support layer by lithography, removing the capping layer via wet etching to leave the support layer intact in the form of a shell having a cavity occupied by the microscopic structure, depositing a layer of meltable material over the capping layer that is thick enough to provide a barrier against gas permeation, but thin enough to leave the vias open, and selectively applying a laser beam to the meltable material proximate each via for a sufficient period of time to melt the material for sealing the via.

5908312, Jun 1, 1999

May 28, 1997

8/864220

Kin Ping Cheung - Hoboken NJ
Steven James Hillenius - Summit NJ
Chun-Ting Liu - Berkeley Heights NJ
Yi Ma - Orlando FL
Pradip Kumar Roy - Orlando FL

Lucent Technologies, Inc. - Murray Hill NJ

H01L 21336

438287

A method of preventing diffusion penetration of the dopant used to dope polysilicon gate material in a MOSFET is disclosed. Atomic nitrogen is introduced into the substrate prior to gate oxide growth. The nitrogen later diffuses upward into the gate oxide and blocks subsequent ion implanted gate dopants from penetrating to the substrate. Low dosages of atomic nitrogen implantation, while not significantly affecting gate oxide growth rate, produce significant improvements in the damage immunity of thin gate oxides.