Kwok Yin Lo, Age 6918716 Everwood Ct, Dallas, TX 75252

Kwok Lo Phones & Addresses

18716 Everwood Ct, Dallas, TX 75252 (817) 522-8396

Missouri City, TX

1706 Hanover Dr, Richardson, TX 75081 (972) 783-0653

Portland, OR

Monterey Park, CA

18716 Everwood Ct, Dallas, TX 75252 (214) 418-7348

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: High school graduate or higher

Mentions for Kwok Yin Lo

Career records & work history

Medicine Doctors

Kwok M. Lo

Specialties:
Hematology/Oncology
Work:
Hematology Oncology PCHematology Oncology
34 Shelburne Rd STE B, Stamford, CT 06902
(203) 325-2695 (phone) (203) 975-7842 (fax)
Site
Education:
Medical School
Harvard Medical School
Graduated: 1985
Procedures:
Bone Marrow Biopsy, Chemotherapy
Conditions:
Bladder Cancer, Gastric Cancer, Hodgkin's Lymphoma, Kidney Cancer, Malignant Neoplasm of Female Breast, Melanoma, Multiple Myeloma, Pancreatic Cancer, Anemia, Breast Neoplasm, Malignant, Cervical Cancer, Hemolytic Anemia, Iron Deficiency Anemia, Laryngeal Cancer, Leukemia, Liver Cancer, Lung Cancer, Malignant Neoplasm of Colon, Malignant Neoplasm of Esophagus, Malignant Neoplasm of Female Genitourinary Organs, Non-Hodgkin's Lymphoma, Ovarian Cancer, Prostate Cancer, Rectal, Abdomen, Small Intestines, or Colon Cancer, Sickle-Cell Disease, Skin Cancer, Testicular Cancer, Thyroid Cancer, Uterine Cancer, Vitamin B12 Deficiency Anemia
Languages:
English, Spanish
Description:
Dr. Lo graduated from the Harvard Medical School in 1985. He works in Stamford, CT and specializes in Hematology/Oncology. Dr. Lo is affiliated with Stamford Hospital.

Kwok Lo resumes & CV records

Resumes

Kwok Lo Photo 15

Kwok Lo

Kwok Lo Photo 16

Kwok Lo

Publications & IP owners

Us Patents

Method And Apparatus For Testing Circuitry With Memory And With Forcing Circuitry

US Patent:
5696770, Dec 9, 1997
Filed:
Oct 18, 1995
Appl. No.:
8/544740
Inventors:
Kwok Yin Lo - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 2900
US Classification:
371 211
Abstract:
A method and apparatus for testing circuits with memories is provided in which a memory array (26) is coupled to memory input logic (33) and memory output logic (34). Furthermore, forcing circuitry (36) is coupled in parallel with memory (26). An automatic test pattern generator transmits test patterns to memory input logic (33) to test its functionality. During testing operations, a memory array (26) is tri-stated. Tri-stating is accomplished by programming the automatic test pattern generator with a model of a tri-stating circuit (38) rather than actual memory array (26). Memory output logic (34) is tested by forcing its inputs through forcing circuitry (36). Forcing circuitry (36) forces the inputs to memory output logic (34) either by receiving a pattern from the automatic test pattern generator or by generating signals based on the outputs from memory input logic (33).

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