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Lee D Gallaher, Age 68149 Nebraska St, Frankfort, IL 60423

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Alex E Dragoo 37 Dorothee Dragoo Elliott R Dragoo 38

Lee Gallaher Phones & Addresses

149 Nebraska St, Frankfort, IL 60423

10300 Village Circle Dr, Palos Park, IL 60464

149 E Nebraska St APT 3, Frankfort, IL 60423

Mentions for Lee D Gallaher

Resumes & CV records

Resumes

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Lee Gallaher

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Lee Gallaher

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Lee Ann Gallaher

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Broker/ Owner Gallaher Real Estate

Position:
Broker/ Owner at Gallaher Real Estate
Location:
Mukilteo, Washington
Industry:
Real Estate
Work:
Gallaher Real Estate - Mukilteo WA since Jun 1992
Broker/ Owner United States Navy - Pear Harbour Hawaii Dec 1978 - Dec 1984
Deep Sea Diver
Skills:
VA, Residential, Real Estate, Foreclosures, Buyer Representation, Single Family Homes, Real Estate Transactions, First Time Buyers, First Time Home Buyers, Purchase, Home, Luxury, HUD, Realty, Distressed Property, Selling, SFR, REO, Brokerage, Resale, Referrals, Contract Negotiation, Investment Properties, Residential Homes, Real Property, Sellers, Property Management, Resellers, Investments, Property, Short Sales, Negotiation, Relocation, Condos, Real Estate Development, Listings, ABR, Investors, Townhomes, New Home Sales, New Homes, Rentals, FHA, Move Up Buyers, Vacation Homes, Waterfront, Income Properties, 1031 Exchanges, Buyers, Home Staging
Interests:
Business, investing, painting fine art, NBA, exercise, weight training, reading, philosophy.
Honor & Awards:
Decca College level Washington State Champion 1985-sales. Remax 100% Club 1988. GRE 200% club 1992.

Publications & IP owners

Us Patents

Cache Arrangement For Direct Memory Access Block Transfer

US Patent:
4504902, Mar 12, 1985
Filed:
Mar 25, 1982
Appl. No.:
6/361499
Inventors:
Lee E. Gallaher - Glen Ellyn IL
Wing N. Toy - Glen Ellyn IL
Benjamin Zee - Glen Ellyn IL
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
G06F 900
G06F 1300
G06F 938
US Classification:
364200
Abstract:
A cache memory system reduces cache interference during direct memory access block write operations to main memory. A control memory within cache contains in a single location validity bits for each word in a memory block. In response to the first word transferred at the beginning of a direct memory access block write operation to main memory, all validity bits for the block are reset in a single cache cycle. Cache is thereafter free to be read by the central processor during the time that the remaining words of the block are written without the need for additional cache invalidation memory cycles.

Possible Relatives

Gilbert A Gallaher  Janet L Gallaher  Jennifer Gallaher  John C Gallaher  Karen L Gallaher  Laura A Gallaher  Leslie E Gallaher  Lee L Standley  Lee L Johnston  Lee Stanford 

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