Li I Song830 Arroyo Ct, Palo Alto, CA 94306

6813572, Nov 2, 2004

Oct 24, 2002

10/281432

Akella V.S. Satya - Milpitas CA
Li Song - Fremont CA
Robert Thomas Long - Santa Cruz CA
Kurt H. Weiner - San Jose CA

KLA-Tencor Technologies Corporation - Milpitas CA

G06F 1900

702 82

Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.

6918101, Jul 12, 2005

Oct 24, 2002

10/281416

Akella V. Satya - Milpitas CA, US
Raman K. Nurani - San Jose CA, US
Li Song - Fremont CA, US

KLA -Tencor Technologies Corporation - Milpitas CA

G06F017/50

716 5, 716 4

Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method for determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function.

6948141, Sep 20, 2005

Oct 24, 2002

10/281427

Akella V. S. Satya - Milpitas CA, US
Vladimir D. Federov - Bellevue WA, US
Li Song - Fremont CA, US

KLA-Tencor Technologies Corporation - Milpitas CA

G06F017/50

716 4, 716 18, 716 21

Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function.

7089516, Aug 8, 2006

Mar 22, 2004

10/806680

Narain D. Arora - San Jose CA, US
Li J. Song - Fremont CA, US
Aki Fujimura - Saratoga CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716 4, 716 5

The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.

7134459, Nov 14, 2006

Jun 3, 2004

10/860113

Eric Carlson - Cupertino CA, US
Li Song - Cupertino CA, US
Daniel M. Pinkas - Alameda CA, US
Claus G. Lugmair - San Jose CA, US

Symyx Technologies, Inc. - Santa Clara CA

B65B 1/04

141130, 141 67, 422100, 406 16, 406 28

Method for preparing a mixed powder sample by mixing two or more different powders comprising transferring a quantity of a first powder to a mixing vessel and transferring a quantity of a second powder to the mixing vessel to form a powder bed in the mixing vessel comprising the first and second powders. The quantities of the powders are selected so the mixed sample has a predetermined ratio of first powder to second powder. The powder bed is fluidized to mix the powders and produce a mixed sample. The mixed sample weighs about 5 grams or less. The invention also includes apparatus for preparing mixed powder samples by mixing two or more different powders.

7507337, Mar 24, 2009

Sep 2, 2005

11/219073

Miroslav Petro - San Jose CA, US
Gary M. Diamond - San Jose CA, US
Thomas Harding McWaid - Fremont CA, US
Keith Anthony Hall - San Jose CA, US
Li Song - Santa Clara CA, US
Trevor G. Frank - Fremont CA, US

Symyx Technologies, Inc. - Sunnyvale CA

B01D 15/08

2101982, 210656, 210101, 210143, 210181

The invention relates to liquid chromatography techniques for rapidly characterizing samples, such as polymer solutions, emulsions and dispersions, and to devices for implementing such techniques. The system includes a design that provides the ability to perform chromatographic separations by using mobile phase composition gradients and temperature gradients during separations. The invention accomplishes this by providing mixing zones for a plurality of fluids as well as heated and chilled feeds feeding the fluids to the mixing zones. Additionally, the system provides the ability to analyze separated components with a detector and/or collect separated fractions into vessels of a fraction collector for further separation and/or analysis.

8136068, Mar 13, 2012

Sep 30, 2008

12/242442

Li J. Song - Fremont CA, US
Srini Doddi - Fremont CA, US
Emmanuel Drego - Los Gatos CA, US
Nickhil Jakatdar - Los Altos CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716110

Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.

8219944, Jul 10, 2012

Jun 23, 2009

12/490063

Li J. Song - Fremont CA, US
Rachid Salik - Sunnyvale CA, US
Hao Ji - San Jose, CN
Taber Smith - Saratoga CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716103, 716104, 716111, 716122, 716123, 716130, 716716, 716132, 716136

A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.