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Liang Wang, Age 61San Jose, CA

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Known as:
Wang Liang
Related to:
Xiaolin Wang Everett 63 Xiaoyi Guo 66 Xi Wang

Liang Wang Phones & Addresses

San Jose, CA

Sunnyvale, CA

Cupertino, CA

Mentions for Liang Wang

Career records & work history

Lawyers & Attorneys

Liang Wang Photo 1

Liang Wang - Lawyer

Licenses:
New York - Currently registered 2012
Education:
The Ohio State University
Liang Wang Photo 2

Liang Wang - Lawyer

Licenses:
California - Active 2001
Specialties:
Mergers / Acquisitions - 50%
Corporate / Incorporation - 50%

Publications & IP owners

Us Patents

Selectively Displaying Surfaces Of An Object Model

US Patent:
8638334, Jan 28, 2014
Filed:
Nov 25, 2008
Appl. No.:
12/323242
Inventors:
Hailin Jin - San Jose CA, US
Liang Wang - Lexington KY, US
Assignee:
Adobe Systems Incorporated - San Jose CA
International Classification:
G06T 15/00
US Classification:
345520, 345419, 345582
Abstract:
Techniques for selectively displaying surfaces of an object model to a user are described. In one embodiment, a computer-implemented method may include, for a given one of a plurality of surfaces included in an object model that is representative of a physical object, determining a normal vector of the given surface. The method may also include determining an angle between the normal vector of the given surface and a current viewing direction of the model. The method may further include displaying the object model to a user without displaying the given surface to the user, dependent upon determining that the angle between the normal vector and the current viewing direction is greater than a threshold value.

High Yield Substrate Assembly

US Patent:
2013012, May 23, 2013
Filed:
May 2, 2012
Appl. No.:
13/462676
Inventors:
Liang Wang - Milpitas CA, US
Ilyas Mohammed - Santa Clara CA, US
Masud Beroz - Morrisville NC, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 29/06
H01L 29/04
H01L 29/12
H01L 33/08
H01L 21/20
US Classification:
257 52, 438 34, 438486, 257618, 257 76, 257E33002, 257E2109, 257E29022, 257E29068, 257E29003
Abstract:
High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Heat Spreading Substrate

US Patent:
2013021, Aug 22, 2013
Filed:
Feb 17, 2012
Appl. No.:
13/399952
Inventors:
Gabriel Z. Guevara - San Jose CA, US
Ilyas Mohammed - Santa Clara CA, US
Liang Wang - Milpitas CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H05K 7/20
G06T 1/00
B05D 5/12
F21V 29/00
US Classification:
345501, 361720, 174252, 362382, 36224902, 427 58
Abstract:
Heat spreading substrate. In accordance with an embodiment of the present invention, an apparatus includes a thermally conductive, electrically insulating regular solid, a first electrically conductive coating mechanically coupled to a first edge of the regular solid and a second electrically conductive coating mechanically coupled to a second edge of the regular solid. The first and the second electrically conductive coatings are electrically isolated from one another and the faces of the first electrically conductive coating, the second electrically conductive coating and the regular solid are substantially co-planar. The primary and secondary surfaces of the regular solid may be free of electrically conductive materials.

High Yield Substrate Assembly

US Patent:
2013028, Oct 31, 2013
Filed:
Jun 3, 2013
Appl. No.:
13/908902
Inventors:
Liang WANG - Milpitas CA, US
Ilyas MOHAMMED - Santa Clara CA, US
Masud BEROZ - Morrisville NC, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 33/00
US Classification:
438 34
Abstract:
High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Quantum Efficiency Of Multiple Quantum Wells

US Patent:
2014000, Jan 9, 2014
Filed:
Jul 3, 2012
Appl. No.:
13/541559
Inventors:
Liang Wang - Milpitas CA, US
Ilyas Mohammed - Santa Clara CA, US
Masud Beroz - Apex NC, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 33/06
US Classification:
257 13, 438 28
Abstract:
Improved quantum efficiency of multiple quantum wells. In accordance with an embodiment of the present invention, an article of manufacture includes a p side for supplying holes and an n side for supplying electrons. The article of manufacture also includes a plurality of quantum well periods between the p side and the n side, each of the quantum well periods includes a quantum well layer and a barrier layer, with each of the barrier layers having a barrier height. The plurality of quantum well periods include different barrier heights.

Parallel Plate Slot Emission Array

US Patent:
2014000, Jan 9, 2014
Filed:
Jul 6, 2012
Appl. No.:
13/543697
Inventors:
Ilyas Mohammed - Santa Clara CA, US
Liang Wang - Milpitas CA, US
Steven D. Gottke - Palo Alto CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 27/15
H01L 33/60
US Classification:
257 88, 438 27
Abstract:
Parallel plate slot emission array. In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection.

Optical Enhancement Of Light Emitting Devices

US Patent:
2014000, Jan 9, 2014
Filed:
Jul 3, 2012
Appl. No.:
13/541615
Inventors:
Liang Wang - Milpitas CA, US
Masud Beroz - Apex NC, US
Ilyas Mohammed - Santa Clara CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 33/58
US Classification:
257 98, 438 29, 257E33067
Abstract:
Optical enhancement of light emitting devices. In accordance with an embodiment of the present invention, an apparatus includes an optical enhancement layer comprising nanoparticles. Each of the nanoparticles includes an electrically conductive core surrounded by an electrically insulating shell. The optical enhancement layer is disposed on a top semiconductor layer in a preferred path of optical emission of a light emitting device. The nanoparticles may enhance the light emission of the light emitting device due to emitter-surface plasmon coupling.

High Performance Light Emitting Diode With Vias

US Patent:
2014001, Jan 16, 2014
Filed:
Dec 31, 2012
Appl. No.:
13/732275
Inventors:
Liang Wang - Milpitas CA, US
Assignee:
INVENSAS CORPORATION - San Jose CA
International Classification:
H01L 33/38
H01L 33/06
US Classification:
257 13, 257 98
Abstract:
High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.

Isbn (Books And Publications)

Historical Outline Of China

Author:
Liang Wang
ISBN #:
0595156908

Possible Relatives

Dawn Y Wang  Dean Y Wang  Deanna Y Wang  Dai H Wang  Daisy H Wang  Debbie Y Wang  Debby Wang  Liang S Liu  Liang C Tai  Liang W Pan 

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