Lizhong H Sun, Age 6110 Sullivan Ln, Acton, MA 01720

6396357, May 28, 2002

May 1, 2000

09/562305

Lizhong Sun - Emmaus PA
Dale Nelson - Macungie PA

Agere Systems Guardian Corp. - Allentown PA

H03B 524

331 57, 331 34, 331177 R, 331185, 327109, 327543

A ring oscillator including a voltage-to-current converter for producing at least one control current from at least one control voltage and, a plurality of delay cells coupled to the converter, wherein at least one output of the one of the delay cells is coupled to the input of another of the delay cells, wherein the voltage-to-current converter produces a substantially linear output when the at least one control voltage is varied between zero volts and a rail supply voltage. Since the ring oscillator operates from a low voltage source, it can be used in applications where power supply (e. g. , battery size) is small (e. g. , pagers, cellular phone applications).

6504437, Jan 7, 2003

Jun 26, 2001

09/891595

Dale H. Nelson - Macungie PA
Lizhong Sun - Budd Lake NJ

Agere Systems Inc. - Allentown PA

H03L 700

331 14, 331 16, 331 17

A phase-lock loop (PLL) circuit provides fast locking and low spurious modulation jitter through âgearshiftingâ control. The gearshifting PLL combines the advantages of low jitter from integer-N PLL and fast locking from fractional-N PLL. The PLL circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). Control of the PLL circuit includes configuring the PLL circuit in two configurations, one for each phase of operation. The bandwidth of the loop filter is increased during the first phase of operation and the circuit is locked to a frequency that is close to the desired output frequency. During the second phase, the bandwidth of the loop filter is decreased and the circuit is locked to the desired frequency. The first configuration provides a relatively fast lock time compared to the lock time provided by the second configuration. The second configuration provides more stability than the first configuration.

6552618, Apr 22, 2003

Dec 13, 2000

09/735699

Dale H. Nelson - Shillington PA
Lizhong Sun - Emmaus PA

Agere Systems Inc. - Allentown PA

H03L 7087

331 11, 331 1 A, 331 17, 331175, 331177 R, 331 34

A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

6946884, Sep 20, 2005

Apr 25, 2002

10/131210

William Eric Holland - Lynchburg City VA, US
Wenzhe Luo - Allentown PA, US
Zhigang Ma - Allentown PA, US
Dale H. Nelson - Macungie PA, US
Harold Thomas Simmonds - Stewartsville NJ, US
Lizhong Sun - Budd Lake NJ, US
Xiangqun Sun - Randolph NJ, US

Agere Systems Inc. - Allentown PA

H03K021/00

327115, 327117, 327157, 331 25, 375376

A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e. g. , 12. 00, 12. 80, 13. 00, 15. 36, 16. 80, 19. 20, 19. 44, 19. 68, 19. 80, and 26. 00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e. g. , 12 or 13 MHz).

7113009, Sep 26, 2006

Mar 24, 2004

10/807852

Lizhong Sun - Nashua NH, US
Bruce Del Signore - Hollis NH, US
Axel Thomsen - Austin TX, US
Douglas F. Pastorello - Hudson NH, US

Silicon Laboratories Inc. - Austin TX

H03K 25/00

327115, 377 47, 377 48

A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.

7187216, Mar 6, 2007

Jun 28, 2004

10/878198

Lizhong Sun - Nashua NH, US
Douglas F. Pastorello - Hudson NH, US
Richard J. Juhn - Nashua NH, US
Axel Thomsen - Austin TX, US

Silicon Laboratories Inc. - Austin TX

H03K 21/00

327115, 327117

A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.

7405601, Jul 29, 2008

Feb 28, 2007

11/680026

Akhil K. Garlapati - Woburn MA, US
Lizhong Sun - Nashua NH, US
Douglas F. Pastorello - Hudson NH, US
Richard J. Juhn - Nashua NH, US
Axel Thomsen - Austin TX, US

Silicon Laboratories Inc. - Austin TX

H03K 21/00

327115, 327117

In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

7471123, Dec 30, 2008

Apr 20, 2005

11/109701

William Eric Holland - Lynchburg City VA, US
Wenzhe Luo - Allentown PA, US
Zhigang Ma - Allentown PA, US
Dale H. Nelson - Macungie PA, US
Harold Thomas Simmonds - Stewartsville NJ, US
Lizhong Sun - Budd Lake NJ, US
Xiangqun Sun - Randolph NJ, US

Agere Systems Inc. - Allentown PA

H03K 21/00

327115, 327117, 327157, 331 25, 375376

A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e. g. , 12. 00, 12. 80, 13. 00, 15. 36, 16. 80, 19. 20, 19. 44, 19. 68, 19. 80, and 26. 00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e. g. , 12 or 13 MHz).