Mark Wayne Gehring, Age 793600 Wallace Rd, Salem, OR 97304

Mark Gehring Phones & Addresses

3600 Wallace Rd, Salem, OR 97304 (503) 371-3530

3700 Wallace Rd, Salem, OR 97304 (503) 371-3530

Keizer, OR

4368 Brush Creek Dr, Silverton, OR 97381 (503) 873-5465 (503) 873-6552

659 Widgeon Rd, Redmond, OR 97756 (541) 548-0550

San Francisco, CA

Post, OR

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Work

Position: Craftsman/Blue Collar

Education

Degree: High school graduate or higher

Mentions for Mark Wayne Gehring

Mark Gehring resumes & CV records

Resumes

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Mark Gehring

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Mark Gehring

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Mark Gehring

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Mark Gehring

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Mark Gehring

Location:
Pompano Beach, Florida
Industry:
Information Technology and Services
Skills:
Enterprise Architecture, IT Strategy, Solution Architecture, Business Intelligence, SDLC, Business Analysis

Publications & IP owners

Us Patents

Voltage Controlled Oscillator

US Patent:
6903613, Jun 7, 2005
Filed:
Dec 20, 2002
Appl. No.:
10/327354
Inventors:
Eric P. Mitchell - Lake Oswego OR, US
Mark R. Gehring - Portland OR, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H03L007/08
H03L007/087
US Classification:
331 11, 331 16, 331 44
Abstract:
Embodiments of the present invention provide a method of centering an operating band of a voltage controlled oscillator around a desired operating frequency. In one embodiment, an adjustable feedback divider provides for driving an output signal to the top and bottom of the operating band. An adjustable period divider and counter provide a plurality of count values for use in determining a mid-point of the operating band. A capacitance bank provides for selectively adjusting a capacitance of the voltage controlled oscillator, thereby adjusting the operating band.

Phase Locked Loop Operable Over A Wide Frequency Range

US Patent:
7109763, Sep 19, 2006
Filed:
Mar 8, 2004
Appl. No.:
10/796873
Inventors:
Nathan Moyal - West Linn OR, US
Eric Mitchell - Lake Oswego OR, US
Mark Gehring - Portland OR, US
Assignee:
Cypress Semiconductor, Corp. - San Jose CA
International Classification:
H03L 7/00
US Classification:
327156, 331 2
Abstract:
A Phase Locked Loop (PLL) that has a substantially constant gain over a wide frequency range. The frequency range over which the PLL operates is divided into a number of frequency sub-ranges. The circuit includes a mechanism for adjusting the loop gain profile as the PLL moves from one frequency sub-range to another. When the PLL switches to a new frequency sub-range, the loop gain profile is adjusted to a pre-established value. Changes of frequency within each sub-range are then accomplished with the loop gain varying within a pre-established range.

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