Mark D Jaffe, Age 62447 Governors Ln, Shelburne, VT 05482

6394638, May 28, 2002

Apr 28, 2000

09/560212

Edward W. Sengle - Hinesburg VT
Mark D. Jaffe - Colchester VT
Daniel Nelson Maynard - Craftsbury Common VT
Mark Alan Lavin - Katonah NY
Eric Jeffrey White - North Farrisburg VT
John A. Bracchitta - So. Burlington VT

International Business Machines Corporation - Armonk NY

H01L 21762

364491, 438129, 438400, 438424, 438439

A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

6870225, Mar 22, 2005

Nov 2, 2001

09/682957

Andres Bryant - Essex Junction VT, US
Mark D. Jaffe - Shelburne VT, US

International Business Machines Corporation - Armonk NY

H01L027/01
H01L027/12
H01L031/0392

257347, 257410, 257411, 257637, 257638, 257640

An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

6943405, Sep 13, 2005

Jul 1, 2003

10/604206

Andres Bryant - Essex Junction VT, US
David M. Fried - Ithaca NY, US
Mark D. Jaffe - Shelburne VT, US
Edward J. Nowak - Essex Junction VT, US
John J. Pekarik - Underhill VT, US
Christopher S. Putnam - Hinesburg VT, US

International Business Machines Corporation - Armonk NY

H01L021/00
H01L029/76

257327, 257329, 257330, 257347, 257350, 257369, 438154, 438157, 438164

A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET.

7098067, Aug 29, 2006

Dec 13, 2004

10/905043

James W. Adkisson - Jericho VT, US
Mark D. Jaffe - Shelburne VT, US
Arthur P. Johnson - Essex Junction VT, US
Robert K. Leidy - Burlington VT, US
Jeffrey C. Maling - Grand Isle VT, US

International Business Machines Corporation - Armonk NY

H01L 21/00

438 75, 257E27133

A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.

7132339, Nov 7, 2006

Dec 9, 2004

11/007843

Andres Bryant - Essex Junction VT, US
Mark D. Jaffe - Shelburne VT, US

International Business Machines Corporation - Armonk NY

H01L 21/36
H01L 21/38

438300, 438269, 438591

An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

7141836, Nov 28, 2006

May 31, 2005

10/908885

James W. Adkisson - Jericho VT, US
Mark D. Jaffe - Shelburne VT, US
Robert K. Leidy - Burlington VT, US

International Business Machines Corporation - Armonk NY

H01L 27/148

257233, 257E27133

A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.

7193289, Mar 20, 2007

Nov 30, 2004

10/904807

James W. Adkisson - Jericho VT, US
Jeffrey P. Gambino - Westford VT, US
Mark D. Jaffe - Shelburne VT, US
Robert K. Leidy - Burlington VT, US
Anthony K. Stamper - Williston VT, US

International Business Machines Corporation - Armonk NY

H01L 27/14

257431, 257432, 257440, 257294, 257292

An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

7193423, Mar 20, 2007

Dec 12, 2005

11/275112

Timothy Joseph Dalton - Ridgefield CT, US
Jeffrey Peter Gambino - Westford VT, US
Mark David Jaffe - Shelburne VT, US
Stephen Ellinwood Luce - Underhill VT, US
Edmund Juris Sprogis - Underhill VT, US

International Business Machines Corporation - Armonk NY

G01R 27/26
G01R 31/02

324662, 324758

Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.