Mark T Kachelmeier, Age 5910190 Harmony Cir, Eden Prairie, MN 55347

Mark Kachelmeier Phones & Addresses

10190 Harmony Cir, Eden Prairie, MN 55347

Austin, TX

Minnetonka, MN

Mentions for Mark T Kachelmeier

Publications

Us Patents

Mos Transistor With Ramped Gate Oxide Thickness

US Patent:
6707112, Mar 16, 2004
Filed:
Jun 4, 2002
Appl. No.:
10/160101
Inventors:
Mark T. Kachelmeier - Austin TX
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 2976
US Classification:
257368, 257411
Abstract:
The invention relates to a transistor having a ramped gate oxide thickness, a semiconductor device containing the same and a method for making a transistor.

Mos Transistor With Ramped Gate Oxide Thickness And Method For Making Same

US Patent:
5741737, Apr 21, 1998
Filed:
Dec 17, 1996
Appl. No.:
8/768883
Inventors:
Mark T. Kachelmeier - Austin TX
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 21336
US Classification:
438286
Abstract:
The invention relates to a transistor having a ramped gate oxide thickness, a semiconductor device containing the same and a method for making a transistor.

Method Of Forming A Non-Volatile Memory Device With Ramped Tunnel Dielectric Layer

US Patent:
5897354, Apr 27, 1999
Filed:
Dec 17, 1996
Appl. No.:
8/768885
Inventors:
Mark T. Kachelmeier - Austin TX
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 21336
US Classification:
438264
Abstract:
The invention relates to a method of forming a non-volatile memory device with a ramped tunnel dielectric layer, in which a floating gate material layer is being oxidized such that a tunnel dielectric layer is formed having a thickness at a drain region edge which is greater than a thickness at a source region edge.

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