Mark KetchenAstoria, NY

8547732, Oct 1, 2013

Jan 10, 2012

13/346847

John F Bulzacchelli - Yonkers NY, US
William J Gallagher - Ardsley NY, US
Mark B Ketchen - Hadley MA, US

International Business Machines Corporation - Armonk NY

G11C 11/00

365158, 365 32, 365 33, 365 46, 365 55, 365 66, 365160, 365162, 365171, 36518919, 36518907, 365189011, 3652255, 36523316, 36523317

In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

8558326, Oct 15, 2013

Mar 27, 2012

13/430906

Stefan Harrer - New York NY, US
Stanislav Polonsky - Putnam Valley NY, US
Mark B. Ketchen - Hadley MA, US
John A. Ott - Greenwood Lake NY, US

International Business Machines Corporation - Armonk NY

H01L 27/14

257414, 438 48, 324 715, 435 61

Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.

8208288, Jun 26, 2012

Mar 27, 2008

12/056788

John F. Bulzacchelli - Yonkers NY, US
William J. Gallagher - Ardsley NY, US
Mark B. Ketchen - Hadley MA, US

International Business Machines Corporation - Armonk NY

G11C 11/00

365158, 365 32, 365 33, 365 46, 365 66, 365160, 365162, 365171, 36518919, 36518907, 365189011, 3652255, 36523316, 36523317

In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

2013030, Nov 14, 2013

Jul 16, 2013

13/943356

William J. GALLAGHER - Ardsley NY, US
Mark B. KETCHEN - Hadley MA, US

G11C 11/16

505170, 365158

In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

5055158, Oct 8, 1991

Apr 4, 1991

7/680441

William J. Gallagher - Ardsley NY
Chao-Kun Hu - Somers NY
Mark A. Jaso - Yorktown Heights NY
Mark B. Ketchen - Hadley MA
Alan W. Kleinsasser - Putnam Valley NY
Dale J. Pearson - Yorktown Heights NY

International Business Machines Corporation - Armonk NY

H01L 21306
B44C 122
C23F 102
C03C 1500

156643

A method for fabricating Josephson integrated circuits and the circuit is described incorporating the steps of depositing layers of different materials to form a trilayer Josephson junction, etching to define a plurality of trilayer areas, depositing dielectric material thereover, and chemical-mechanical polishing to planarize the dielectric material down to provide a coplanar surface with the tops of the trilayer areas for subsequent interconnection. The invention overcomes the problem of poor quality Josephson junctions, low Vm's, and crevices or gaps in the upper coplanar surface between the trilayer area and the surrounding dielectric material.

4851767, Jul 25, 1989

Jan 15, 1988

7/144215

Jean-Marc Halbout - Larchmont NY
Mark B. Ketchen - Hadley MA
Paul A. Moskowitz - Yorktown Heights NY
Michael R. Scheuermann - Somers NY

International Business Machines Corporation - Armonk NY

G01R 3102

324158P

A testing or sampling probe to determine the response of electrical circuits or devices to ultrafast electrical pulses. The probe is detachable from the device being tested. The probe includes a transparent substrate though which optical pulses are focused or directed onto a photoconducting gap. The probe further includes a transmission line associated with the photoconductive gap, and which terminates at a tapered end of the probe in contacts which are placed on the device under test.