Mark Andrew Krom, Age 462300 Picadilly Cir, Longmont, CO 80503

7930484, Apr 19, 2011

Feb 7, 2005

11/052432

Stephen P. Thompson - Longmont CO, US
Mark A. Krom - Longmont CO, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 12/14

711125, 711129, 711134, 711163, 711E12075, 711 E9033

Instructions involving a relatively significant data transfer or a particular type of data transfer via a cache result in the application of a restricted access policy to control access to one or more partitions of the cache so as to reduce or prevent the overwriting of data that is expected to be subsequently used by the cache or by a processor. A processor or other system component may assert a signal which is utilized to select between one or more access policies and the selected access policy then may be applied to control access to one or more ways of the cache during the data transfer operation associated with the instruction. The access policy typically represents an access restriction to particular cache partitions, such as a restriction to one or more particular cache ways or one or more particular cache lines.

8432409, Apr 30, 2013

Dec 23, 2005

11/317593

Frederick S. Dunlap - Longmont CO, US
Mark A. Krom - Longmont CO, US
Adam Snay - Longmont CO, US

G09G 5/37
G06F 13/00

345562, 345537, 345561

A computer readable medium embodies a set of instructions. The set of instructions includes an instruction to manipulate a processor to determine a first value representative of a source memory location of a source storage component, a second value representative of a destination memory location of a destination storage component, a third value representative of a number of lines of a data block to be transferred from the source storage component to the destination storage component, a fourth value representative of a number of bytes to be transferred per line of the data block, a fifth value representative of a byte width of the source storage component and a sixth value representative of a byte width of the destination storage component. The instruction further is to transfer a data block from the source storage component to the destination storage component based on the first, second, third, fourth, fifth and sixth values.

2012004, Feb 23, 2012

Aug 23, 2010

12/861590

Mark Krom - Boulder CO, US
Neal Countryman - Boulder CO, US

QUALCOMM Incorporated - San Diego CA

G06F 3/00
G06F 13/24

710 5, 710 48

In general, this disclosure describes techniques that allow communication between devices/modules of a computer system regarding inter-device/module command execution. In accordance with the techniques described herein, an operating device of a computing system may receive from a client one or more command indications of commands to be executed on the operating device. The operating device may further receive at least one command completion indicator that indicates a command for which one or more clients are awaiting completion of execution. The operating device may generate an interrupt that indicates completion of execution of the command for which the at least one command completion indicator was received. The interrupt may be a generic interrupt or a client-specific interrupt. In this manner, inefficiencies caused by client monitoring of operating device command execution may be reduced.