Mark Werkheiser, Age 49Georgetown, TX

2013004, Feb 14, 2013

Aug 8, 2011

13/137357

Jamshed Jalal - Austin TX, US
Mark David Werkheiser - Austin TX, US
Brett Stanley Feero - Austin TX, US
Michael Alan Filippo - Driftwood TX, US

ARM LIMITED - Cambridge

G06F 12/08

711130, 711E12038, 711E12033

A data processing system includes a cache hierarchy having a plurality of local cache memories and a shared cache memory State data stored within the shared cache memory on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.

2013004, Feb 14, 2013

Aug 8, 2011

13/137359

Jamshed Jalal - Austin TX, US
Brett Stanley Feero - Austin TX, US
Mark David Werkheiser - Austin TX, US
Michael Alan Filippo - Driftwood TX, US

G06F 12/08

711146, 711E12033

A data processing apparatus includes a plurality of transaction sources each including a local cache memory. A shared cache memory stores cache lines of data together with shared cache tag values. Snoop filter circuitry stores snoop filter tag values tracking which cache lines of data are stored within the local cache memories. When a transaction is received for a target cache line of data, then the snoop filter circuitry compares the target tag value with the snoop filter tag values and the shared cache circuitry compares the target tag value with the shared cache tag values. The shared cache circuitry operates in a default non-inclusive mode. The shared cache memory and the snoop filter accordingly behave non-inclusively in respect of data storage within the shared cache memory but inclusively in respect of tag storage given the combined action of the snoop filter tag values and the shared cache tag values. Tag maintenance operations moving tag values between the snoop filter circuitry and the shared cache memory are performed atomically. The snoop filter circuitry and the shared cache memory compare operations are performed using interlocked parallel pipelines.

2013004, Feb 14, 2013

Aug 8, 2011

13/137362

Jamshed Jalal - Austin TX, US
Mark David Werkheiser - Austin TX, US
Brett Stanley Feero - Austin TX, US
Michael Alan Filippo - Driftwood TX, US
Ramamoorthy Guru Prasadh - Austin TX, US
Phanindra Kumar Mannava - Austin TX, US

ARM Limited - Cambridge

G06F 9/46

718103

An integrated circuit includes a plurality of transaction sources communicating via a ring-based interconnect with shared caches each having an associated POC/POS and serving as a request servicing circuit. The request servicing circuits have a set of processing resources that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

2013004, Feb 14, 2013

Aug 8, 2011

13/137360

Jamshed Jalal - Austin TX, US
Mark David Werkheiser - Austin TX, US
Brett Stanley Feero - Austin TX, US
Ramamoorthy Guru Prasadh - Austin TX, US
Michael Alan Filippo - Driftwood TX, US
Phanindra Kumar Mannava - Austin TX, US

ARM LIMITED - Cambridge

G06F 9/50

718104

An integrated circuit includes a plurality of transaction sources communicating via a ring-based interconnect with shared caches each having an associated POC/POS and serving as a request servicing circuit. The request servicing circuits have a set of processing resources that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

2022035, Nov 3, 2022

Apr 29, 2021

17/244182

- Cambridge, GB
Mark David Werkheiser - Austin TX, US
Jamshed Jalal - Austin TX, US
Sai Kumar Marri - Austin TX, US
Ashok Kumar Tummala - Cedar Park TX, US
Rishabh Jain - Austin TX, US

Arm Limited - Cambridge

G06F 13/42
G06F 13/40

The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

2022030, Sep 29, 2022

Mar 25, 2021

17/212804

- Cambridge, GB
Jamshed Jalal - Austin TX, US
Tushar P Ringe - Austin TX, US
Mark David Werkheiser - Austin TX, US
Premkishore Shivakumar - Austin TX, US
Lauren Elise Guckert - Austin TX, US

Arm Limited - Cambridge

G06F 12/0815
G06F 13/40

A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

2021014, May 20, 2021

Nov 15, 2019

16/685082

- Cambridge, GB
Jamshed JALAL - Austin TX, US
Gurunath RAMAGIRI - Austin TX, US
Ashok Kumar TUMMALA - Cedar Park TX, US
Mark David WERKHEISER - Austin TX, US

G06F 13/40
G06F 9/46

An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

2021010, Apr 8, 2021

Oct 4, 2019

16/592979

- Cambridge, GB
Mark David WERKHEISER - Austin TX, US
Phanindra Kumar MANNAVA - Austin TX, US
Bruce James MATHEWSON - Papworth Everard, GB

G06F 9/46
G06F 9/455
G06F 9/38
G06F 13/40
G06F 12/10
G06F 12/0891

Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.