Matthew Scott Deig, Age 484245 Maryland St, San Diego, CA 92103

Matthew Deig Phones & Addresses

4245 Maryland St, San Diego, CA 92103

1740 Sunset Cliffs Blvd, San Diego, CA 92107

3522 Kite St, San Diego, CA 92103

4611 Tivoli St, San Diego, CA 92107

6165 Greenwich Dr, San Diego, CA 92122

West Lafayette, IN

Chandler, AZ

4727 49Th St, San Diego, CA 92115

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Matthew Deig Photo 11

Cad Manager At Peregrine Semiconductor

Location:
Greater San Diego Area
Industry:
Telecommunications
Experience:
Peregrine Semiconductor (Privately Held; Semiconductors industry): CAD Manager,  (March 2010-Present) Qualcomm (Public Company; 10,001+ employees; QCOM; Telecommunications industry): Senior Staff Engineer/Manager,  (December 2006-March 2010) RFMD&n...

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Us Patents

Vertically-Aligned And Conductive Dummies In Integrated Circuit Layers For Capacitance Reduction And Bias Independence And Methods Of Manufacture

US Patent:
2021034, Nov 4, 2021
Filed:
Jul 7, 2021
Appl. No.:
17/369563
Inventors:
- San Diego CA, US
Anil Kumar Vemulapalli - Milpitas CA, US
Matthew Deig - San Diego CA, US
International Classification:
H01L 23/64
H01L 21/84
H01L 27/12
H01L 23/00
Abstract:
Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency ICs.

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