Michael J Schroeder DeceasedPlano, TX

7216205, May 8, 2007

Jan 12, 2004

10/756436

Christopher Alan Greer - Allen TX, US
Michael Alex Schroeder - Dallas TX, US
Gary Belgrave Gostin - Plano TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 12/00

711147, 711169, 707200, 707201, 709205, 709212, 709213, 709230, 709232, 712225

Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.

7406091, Jul 29, 2008

Jan 12, 2004

10/756668

Michael A. Schroeder - Dallas TX, US
Craig W. Warner - Addison TX, US
Gary Belgrave Gostin - Plano TX, US
Mark Edward Shaw - Garland TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04L 12/28
H03M 13/00
G06F 15/173

370432, 370389, 370392, 709238, 714756

Distributing communications between paths, comprises providing a plurality of destinations, providing a plurality of communications paths such that each of the plurality of destinations can be accessed over each of the plurality of communications paths, defining destination addresses interleaved over the plurality of destinations, sending communications from a source to a plurality of the interleaved addresses, and selecting different ones of the plurality of paths for successive communications that are sent to addresses on different destinations, wherein the path for a communication is selected using at least a part of the address of the communication.

7577890, Aug 18, 2009

Jan 21, 2005

11/040380

Michael A. Schroeder - Plano TX, US
Christopher Michael Brueggen - Allen TX, US
Gary B. Gostin - Plano TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04L 1/18

714748, 714776, 714758, 714799

Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure. The system may also comprise an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.

7719996, May 18, 2010

Sep 25, 2006

11/534903

Michael Schroeder - Richardson TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G01R 31/08
G06F 1/04
H04L 9/32
G06G 1/00

370252, 713502, 713178, 713501

A logging system comprising counting logic adapted to generate a raw timestamp. The system further comprises encoding logic coupled to the counting logic and adapted to insert a group of bits of the raw timestamp into a predetermined timestamp template to produce an encoded timestamp. The template is selected based on a position of a most significant bit of the raw timestamp.

7774652, Aug 10, 2010

Sep 19, 2006

11/523472

Richard Adkisson - Plano TX, US
Michael Schroeder - Plano TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G01R 31/3177

714 37, 714812

A system may comprise a condition detection system that includes change circuitry configured to detect a change for at least one predetermined bit of an N-bit bus, where N is a positive integer, and to provide a corresponding change signal indicative of the detected condition. Match circuitry is configured to detect a match condition for up to a selected subset of predetermined bits of the N-bit bus and to provide a corresponding match signal indicative of the detected condition. Selection circuitry is programmable to provide a selected one of the change signal and the match signal as a corresponding output signal.

2006002, Feb 2, 2006

Jul 29, 2004

10/902341

Gary Gostin - Plano TX, US
Larry McMahan - Fremont CA, US
Michael Schroeder - Dallas TX, US
Craig Warner - Addison TX, US
Richard Adkisson - Dallas TX, US
David Binford - Allen TX, US
Mark Shaw - Garland TX, US
Joe Cowan - Ft. Collins CO, US
Thierry Fevrier - Gold River CA, US
Arad Rostampour - Ft. Collins CO, US

G06F 15/16

709245000

A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

2008025, Oct 16, 2008

Apr 11, 2007

11/733857

Craig Warner - Addison TX, US
Dan Robinson - Allen TX, US
John Wastlick - Allen TX, US
Michael Schroeder - Plano TX, US

G06F 12/16

711152

Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.

2017015, Jun 1, 2017

Nov 30, 2016

15/364706

- GOLDEN CO, US
Michael SCHROEDER - Golden CO, US

ENVY SNOW SPORTS LLC - GOLDEN CO

A63C 9/00
A63C 9/22
A43B 5/04

A ski boot frame that is attachable to a soft shell snow boot, for example a snowboard boot, for downhill skiing. The ski boot frame is constructed of multiple rigid materials to provide a user with proper support for downhill skiing. The ski boot frame further includes adjustable toe clip and heel clips for attachment to a standard downhill ski binding. The toe and heel clips are preferably adjustable to fit the frame to a plurality of sizes of ski bindings. The ski boot frame further includes a calf support that provides for a progressive forward resistance critical for downhill skiing.