Michael J Ball, Age 643507 Yachtclub Ct, Arlington, TX 76016

2019020, Jul 4, 2019

Dec 30, 2017

15/859492

- Dallas TX, US
Michael Allen Ball - Richardson TX, US
Jarvis Benjamin Jacobs - Murphy, IN
James Robert Todd - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H01L 29/66
H01L 21/265
H01L 29/167
H01L 21/8238
H01L 29/10
H01L 21/02
H01L 29/45
H01L 21/285
H01L 21/3213
H01L 21/762
H01L 29/417
H01L 29/06
H01L 29/08
H01L 27/092

An integrated circuit having silicide block integrated with CMOS transistors is formed by forming a silicide block layer of primarily silicon dioxide, free of silicon nitride and silicon oxy-nitride, at less than 400 C. prior to annealing the PMOS sources and drains. A spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The NMOS drain junctions are less than 120 nanometers; the NMOS halo regions include boron. The NMOS and PMOS transistors are laterally separated by an STI oxide layer. A wet deglaze process prior to metal silicide formation removes less than 25 percent of the silicide block layer, and exposes sides of the NMOS drains less than 20 percent of the drain junction depth. The metal silicide does not extend down the NMOS drains sides, directly adjacent to the STI oxide layer, more than 20 percent of the drain junction depth.

2018004, Feb 8, 2018

Oct 19, 2017

15/787905

- Dallas TX, US
Richard Allen Bailey - Richardson TX, US
Archana Venugopal - Dallas TX, US
John Anthony Rodriguez - Dallas TX, US
Michael Allen Ball - Richardson TX, US

G11C 17/18
G11C 17/16

A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

2017001, Jan 19, 2017

May 4, 2016

15/146049

- Dallas TX, US
Richard Allen Bailey - Richardson TX, US
Archana Venugopal - Dallas TX, US
John Anthony Rodriguez - Dallas TX, US
Michael Allen Ball - Richardson TX, US

G11C 17/18
G11C 17/16

A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.