Michael Y Chung, Age 463812 Welshland St, Danville, CA 94506

6622230, Sep 16, 2003

Nov 28, 2000

09/724675

Masaru Yano - Sunnyvale CA
Shane Hollmer - San Jose CA
Michael Chung - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

G06F 1206

711209, 711 5, 711103, 36523003

A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block first bit location which is the most significant bit location where the starting and ending addresses have different bits. The method then generates a converted memory block address where bits more significant than the multi-block first bit location are the ending address bits and where bits less significant than, or equal in significance to, the multi-block first bit location are equal to a logic 1. The method also generates a converted complementary memory block address identical to the other converted address except that bits in the bit locations more significant than the multi-block first bit location are the complements of the ending address bits. The method then pre-decodes the two converted addresses to generate sets of pre-decoded z-signals corresponding to the block addresses included in a group of the starting and ending addresses and all the addresses between them. Finally, the method decodes the pre-decoded z-signals to generate signals selecting memory blocks whose addresses are in that group.

5852576, Dec 22, 1998

Oct 6, 1997

8/944904

Binh Quang Le - Mountain View CA
Shane Charles Hollmer - San Jose CA
Shoichi Kawamura - Sunnyvale CA
Michael Shingche Chung - San Jose CA
Vincent C. Leung - Mountain View CA
Masaru Yano - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa-ken

G11C 1300

36518533

Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them.

2019008, Mar 21, 2019

Jun 29, 2018

16/023729

- San Jose CA, US
William H. Vaughan - Redwood City CA, US
Michael Jae-Yoon Chung - San Jose CA, US

G05D 1/02

Disclosed are robot configuration-based mapping and planning technologies for a mobile robot.