Career records & work history
Medicine Doctors
Ming Ding
Specialties:
Anesthesiology
Ming Hui Ding, Age 5014768 Nelson Way, San Jose, CA 95124
Ming Ding Phones & Addresses
San Jose, CA
Las Vegas, NV
Framingham, MA
1661 32Nd St, Allentown, PA 18103 (610) 797-7189
Lexington, KY
14768 Nelson Way, San Jose, CA 95124
Work
Position:
Medical Professional
Education
Degree:
High school graduate or higher
Mentions for Ming Hui Ding
Ming Ding resumes & CV records
Resumes
Ming Ding
Location:
United States
Publications & IP owners
Us Patents
Programmable Logic Devices With Integrated Standard-Cell Logic Blocks
US Patent:
6975137, Dec 13, 2005
Filed:
Feb 10, 2005
Appl. No.:
11/055280
Inventors:
John A. Schadt - Bethlehem PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G06F007/38
G06F017/50
H03K019/177
H03K019/00
G06F017/50
H03K019/177
H03K019/00
US Classification:
326 39, 716 16
Abstract:
A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.
Programmable Logic Device Architecture With Multiple Slice Types
US Patent:
7378872, May 27, 2008
Filed:
Jun 2, 2006
Appl. No.:
11/445620
Inventors:
Om P. Agrawal - Los Altos CA, US
Barry Britton - Orefield PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Barry Britton - Orefield PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/177
US Classification:
326 41, 326 37, 326 38, 326 39, 326 47
Abstract:
Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.
Dual Slice Architectures For Programmable Logic Devices
US Patent:
7385417, Jun 10, 2008
Filed:
Jun 2, 2006
Appl. No.:
11/446542
Inventors:
Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G06F 7/38
H03K 19/173
H03K 19/173
US Classification:
326 39, 326 41, 326 47
Abstract:
Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.
Logic Block Control Architectures For Programmable Logic Devices
US Patent:
7397276, Jul 8, 2008
Filed:
Jun 2, 2006
Appl. No.:
11/446351
Inventors:
Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/177
US Classification:
326 41, 326 38, 326 39, 326 47
Abstract:
Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.
Logic Block Control Architectures For Programmable Logic Devices
US Patent:
7592834, Sep 22, 2009
Filed:
Jun 30, 2008
Appl. No.:
12/164265
Inventors:
Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/173
US Classification:
326 38, 326 40, 326 41, 326 47
Abstract:
In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.
Area Efficient Routing Architectures For Programmable Logic Devices
US Patent:
7605606, Oct 20, 2009
Filed:
Aug 3, 2006
Appl. No.:
11/498646
Inventors:
Ming H. Ding - San Jose CA, US
Sajitha Wijesuriya - Macungie PA, US
Jun Zhao - Allentown PA, US
Om P. Agrawal - Los Altos CA, US
Barry Britton - Orefield PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Jun Zhao - Allentown PA, US
Om P. Agrawal - Los Altos CA, US
Barry Britton - Orefield PA, US
Xiaojie He - Austin TX, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/177
US Classification:
326 41, 326 38
Abstract:
Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.
Dual-Slice Architectures For Programmable Logic Devices
US Patent:
7675321, Mar 9, 2010
Filed:
Mar 24, 2009
Appl. No.:
12/409757
Inventors:
Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H01L 25/00
G06F 7/38
G06F 7/38
US Classification:
326 41, 326 38, 326 40, 326 47
Abstract:
In one embodiment of the invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within a programmable logic block. A dual-slice logic block includes a first slice including at least two lookup tables (LUTs); a second slice including at least two LUTs; and a routing circuit coupled to each of the LUTs within the first and second slices. The routing circuit is adapted to share outputs of the dual-slice logic block among the LUTs. In another embodiment of the invention, the dual-slice logic block includes a second routing circuit coupled to each of the LUTs within the first and second slices. The second routing circuit is adapted to share inputs of the dual-slice logic block among the LUTs.
Programmable Logic Device With Multiple Slice Types
US Patent:
7696784, Apr 13, 2010
Filed:
Apr 18, 2008
Appl. No.:
12/105959
Inventors:
Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/177
US Classification:
326 41, 326 40
Abstract:
In one embodiment, a programmable logic device includes a plurality of programmable logic blocks and a plurality of slices within each of the programmable logic blocks. At least one programmable logic blocks includes a first slice not adapted to provide register functionality or RAM functionality, a second slice adapted to provide register functionality but not RAM functionality, and a third slice adapted to provide register functionality and RAM functionality. Control logic within the programmable logic block is adapted to provide control signals at the programmable block level and at the slice level.
Amazon
Multi-Point Cooperative Communication Systems: Theory And Applications (Signals And Communication Technology)
Author:
Ming Ding, Hanwen Luo
Publisher:
Springer
Binding:
Hardcover
Pages:
280
ISBN #:
364234948X
EAN Code:
9783642349485
Multi-point Cooperative Communication Systems: Theory and Applications mainly discusses multi-point cooperative communication technologies which are used to overcome the long-standing problem of limited transmission rate caused by the inter-point interference. Instead of combating the interference, ...
The Five Body Copy Of Pen Calligraphy (Chinese Edition)
Author:
Ding Qi Ming
Publisher:
New Times Press
Binding:
Paperback
Pages:
251
ISBN #:
7504210846
EAN Code:
9787504210845
Guidebook To Chen-Style Tai Chi Kung Fu (Chinese Edition)
Author:
ding ming ye
Publisher:
People's Sports Press
Binding:
Paperback
Pages:
384
ISBN #:
7500933312
EAN Code:
9787500933311
Many martial artists believe that Mr. Hong Junshengs contribution to Chen-style Tai Chi lies in the fact that he has made a creative study of twining strength of spiral movement and put forward the brilliant theory of Tai Chi is a burst of jabbing action in a spiral manner. He has summed up the move...
Preschool Tracing Chinese Characters: Learning Basic Chinese 1 (Chinese Edition)
Author:
Li Li Qiang, Chen Ling, Zhan Ding Ming
Publisher:
21th Century Publishing House
Binding:
Paperback
Pages:
199
ISBN #:
7539173815
EAN Code:
9787539173818
The series consists of 20 books covering all learning and writing content that preschool children shall grasp, such as Chinese, mathematics, English, and art, etc. All these books are compiled according to the lasts curriculum standards for primary school step by step and linking preschool and prima...
Preschool Tracing Chinese Characters: Learning Common Chinese 2 (Chinese Edition)
Author:
Li Li Qiang, Chen Ling, Zhan Ding Ming
Publisher:
21th Century Publishing House
Binding:
Paperback
Pages:
199
ISBN #:
7539173807
EAN Code:
9787539173801
The series consists of 20 books covering all learning and writing content that preschool children shall grasp, such as Chinese, mathematics, English, and art, etc. All these books are compiled according to the lasts curriculum standards for primary school step by step and linking preschool and prima...
Possible Relatives
NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.