Narendra N Sankar, Age 52Bradenton, FL

6389449, May 14, 2002

Mar 22, 1999

09/273810

Mario D. Nemirovsky - Saratoga CA
Adolfo M. Nemirovsky - San Jose CA
Narendra Sankar - Santa Clara CA

Clearwater Networks, Inc. - Los Gatos CA

G06F 900

709108, 712228

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map.

6477562, Nov 5, 2002

Dec 16, 1998

09/216017

Mario D. Nemirovsky - Saratoga CA
Adolfo M. Nemirovsky - San Jose CA
Narendra Sankar - Santa Clara CA

Clearwater Networks, Inc. - Los Gatos CA

G06F 900

709108, 712 23

A multi-streaming processor has multiple streams for processing multiple threads, and an instruction scheduler including a priority record of priority codes for one or more of the streams. The priority codes determine in some embodiments relative access to resources as well as which stream has access at any point in time. In other embodiments priorities are determined dynamically and altered on-the-fly, which may be done by various criteria, such as on-chip processing statistics, by executing one or more priority algorithms, by input from off-chip, according to stream loading, or by combinations of these and other methods. In one embodiment a special code is used for disabling a stream, and streams may be enabled and disabled dynamically by various methods, such as by on-chip events, processing statistics, inpu from off-chip, and by processor interrupts. Some specific applications are taught, including for IP-routers and digital signal processors.

6789100, Sep 7, 2004

Feb 8, 2002

10/071547

Mario D. Nemirovsky - Saratoga CA
Adolfo M. Nemirovsky - San Jose CA
Narendra Sankar - Santa Clara CA

MIPS Technologies, Inc. - Mountain View CA

G06J 900

709107, 713 1, 712 23

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map.

7020879, Mar 28, 2006

May 14, 1999

09/312302

Mario D. Nemirovsky - Saratoga CA, US
Adolfo M. Nemirovsky - San Jose CA, US
Narendra Sankar - Santa Clara CA, US

MIPS Technologies, Inc. - Mountain View CA

G06F 9/46
G06F 15/76

718107, 712 23

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt.

7032226, Apr 18, 2006

Jun 30, 2000

09/608750

Mario Nemirovsky - Saratoga CA, US
Narendra Sankar - Santa Clara CA, US
Adolfo Nemirovsky - San Jose CA, US
Enric Musoll - San Jose CA, US

MIPS Technologies, Inc. - Mountain View CA

G06F 9/46

719318, 719313, 719314, 719315, 719316, 719317, 718103, 718104, 718106, 718107, 710 22, 709213, 711147

A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.

7058064, Jun 6, 2006

Dec 14, 2000

09/737375

Mario Nemirovsky - Saratoga CA, US
Enric Musoll - San Jose CA, US
Stephen Melvin - San Francisco CA, US
Narendra Sankar - Santa Clara CA, US
Nandakumar Sampath - Santa Clara CA, US
Adolfo Nemirovsky - San Jose CA, US

MIPS Technologies, Inc. - Mountain View CA

H04L 12/56
G06F 13/00
G06F 12/00

3703957, 370412, 710 52, 710310, 711154, 711170

In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

7139898, Nov 21, 2006

Nov 3, 2000

09/706154

Mario Nemirovsky - Saratoga CA, US
Adolfo Nemirovsky - San Jose CA, US
Narendra Sankar - Campbell CA, US
Enrique Musoll - San Jose CA, US

Mips Technologies, Inc. - Mountain View CA

G06F 9/312

712206

A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.

7406586, Jul 29, 2008

Oct 6, 2006

11/539322

Mario Nemirovsky - Saratoga CA, US
Adolfo Nemirovsky - San Jose CA, US
Narendra Sankar - Campbell CA, US
Enrique Musoll - San Jose CA, US

MIPS Technologies, Inc. - Mountain View CA

G06F 9/30

712215

A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.