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Nelson N Chan, Age 53926 John Murray Way, Folsom, CA 95630

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Known as:
Nelson Nai Chan Nai Ying Chan Nai N Chan Nai Y Chan Naiying Y Chan Nai Chan Nelson Ying Chan Nai-Ying Chan Naiying Channai Nai Han Naiy Chan
Related to:
Yiui Lin

Nelson Chan Phones & Addresses

926 John Murray Way, Folsom, CA 95630 (916) 608-9577

1015 Folsom Ranch Dr #103, Folsom, CA 95630

7940 La Riviera Dr #212, Sacramento, CA 95826 (916) 383-9122

212 La Riviera Dr #7940, Sacramento, CA 95826

1715 W Magnolia Ln, Mount Prospect, IL 60056

Ann Arbor, MI

Arlington Heights, IL

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Work

Address: 2218 Kausen Dr #100, Elk Grove, CA 95758 Specialities: Fraud - 100%

Education

School / High School: University of California - Davis

Ranks

Licence: California - Active Date: 1983

Mentions for Nelson N Chan

Career records & work history

Lawyers & Attorneys

Nelson Chan Photo 1

Nelson Chan - Lawyer

ISLN:
908446573
Admitted:
1976
University:
University of Pennsylvania, B.A.
Law School:
University of Pennsylvania, J.D.
Nelson Chan Photo 2

Nelson Chan - Lawyer

Specialties:
Business Litigation, Business Formation, Real Estate Law, Mechanics Liens, Director and Officer Liability, Water Law, Public Law, Consumer Protection, Consumer Protection
ISLN:
909721662
Admitted:
1983
University:
University of California at Davis, A.B., 1980
Law School:
Hastings College of the Law, University of California, J.D., 1983
Nelson Chan Photo 3

Nelson Howe Chan, Elk Grove CA - Lawyer

Address:
2218 Kausen Dr #100, Elk Grove, CA 95758
(916) 478-7272 (Office)
Licenses:
California - Active 1983
Education:
University of California - Davis
University of California, Hastings College of the Law
Specialties:
Fraud - 100%
Nelson Chan Photo 4

Nelson H. Chan, Elk Grove CA - Lawyer

Office:
2218 Kausen Dr., Ste. 100, Elk Grove, CA
ISLN:
909721662
Admitted:
1983
University:
University of California, A.B.
Law School:
University of California, Hastings College of the Law, J.D.
Nelson Chan Photo 5

Nelson Howe Chan, Elk Grove CA - Lawyer

Address:
2218 Kausen Dr, Elk Grove, CA 95758
Phone:
(916) 478-7272 (Phone), (916) 478-7331 (Fax)
Experience:
42 years
Jurisdiction:
California (1983)
Law School:
UC Hastings COL
Education:
Univ of California Davis, Undergraduate Degree
UC Hastings COL, Law Degree
Memberships:
California State Bar (1983)

Nelson Chan resumes & CV records

Resumes

Nelson Chan Photo 29

Principal Engineer

Location:
Folsom, CA
Industry:
Semiconductors
Work:
Intel Corporation
Principal Engineer Soft Machines May 2006 - Sep 2016
Founding Engineer and Senior Staff Engineer and Uarchitect Intel Corporation Feb 1998 - May 2006
Senior Engineer
Education:
University of Michigan 1996 - 1997
Masters, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science Illinois Institute of Technology 1994 - 1995
Masters, Computer Engineering National Taiwan University 1990 - 1994
Bachelors, Physics Chien - Kuo Senior High School 1987 - 1990
Skills:
Microprocessors, X86, Computer Architecture, Rtl Design, Verilog, Asic, Vlsi, Soc, Debugging, Processors, Semiconductors, Ic, Static Timing Analysis, C, Perl, Very Large Scale Integration
Languages:
English
Nelson Chan Photo 30

Nelson Chan

Nelson Chan Photo 31

Nelson Chan

Nelson Chan Photo 32

Nelson Chan

Location:
United States

Publications & IP owners

Us Patents

Method And Apparatus For Efficient Scheduling For Asymmetrical Execution Units

US Patent:
2017019, Jul 13, 2017
Filed:
Mar 24, 2017
Appl. No.:
15/469460
Inventors:
- Santa Clara CA, US
Nelson N. CHAN - Folsom CA, US
International Classification:
G06F 9/38
Abstract:
A method and system performs instruction scheduling in an out-of-order microprocessor pipeline. The method and system selects a first set of instructions to dispatch from a scheduler to an execution module, wherein the execution module comprises two types of execution units. The first type of execution unit executes both a first and a second type of instruction and the second type of execution unit executes only the second type. Next, the method selects a second set of instructions to dispatch, which is a subset of the first set and comprises only instructions of the second type. The method determines a third set of instructions, which comprises instructions not selected as part of the second set. Further, the method dispatches the second set for execution using the second type of execution unit and dispatching the third set for execution using the first type of execution unit.

Method And Apparatus To Avoid Deadlock During Instruction Scheduling Using Dynamic Port Remapping

US Patent:
2016033, Nov 17, 2016
Filed:
Jul 25, 2016
Appl. No.:
15/219119
Inventors:
- Santa Clara CA, US
Nelson N. CHAN - Folsom CA, US
International Classification:
G06F 9/38
G06F 9/30
Abstract:
A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor is disclosed. The method comprises selecting and dispatching a plurality of instructions from a plurality of select ports in a scheduler module in first clock cycle. Next, it comprises determining if a first physical register file unit has capacity to support instructions dispatched in the first clock cycle. Further, it comprises supplying a response back to logic circuitry between the plurality of select ports and a plurality of execution ports, wherein the logic circuitry is operable to re-map select ports in the scheduler module to execution ports based on the response. Finally, responsive to a determination that the first physical register file unit is full, the method comprises re-mapping at least one select port connecting with an execution unit in the first physical register file unit to a second physical register file unit.

Method And Apparatus For Efficient Scheduling For Asymmetrical Execution Units

US Patent:
2014037, Dec 18, 2014
Filed:
Dec 16, 2013
Appl. No.:
14/107116
Inventors:
- Santa Clara CA, US
Nelson N. CHAN - Folsom CA, US
Assignee:
Soft Machines, Inc. - Santa Clara CA
International Classification:
G06F 9/48
G06F 9/38
US Classification:
718103
Abstract:
A method for performing instruction scheduling in an out-of-order microprocessor pipeline is disclosed. The method comprises selecting a first set of instructions to dispatch from a scheduler to an execution module, wherein the execution module comprises two types of execution units. The first type of execution unit executes both a first and a second type of instruction and the second type of execution unit executes only the second type. Next, the method comprises selecting a second set of instructions to dispatch, which is a subset of the first set and comprises only instructions of the second type. Next, the method comprises determining a third set of instructions, which comprises instructions not selected as part of the second set. Finally, the method comprises dispatching the second set for execution using the second type of execution unit and dispatching the third set for execution using the first type of execution unit.

Method And Apparatus To Avoid Deadlock During Instruction Scheduling Using Dynamic Port Remapping

US Patent:
2014028, Sep 18, 2014
Filed:
Dec 10, 2013
Appl. No.:
14/101615
Inventors:
- Santa Clara CA, US
Nelson N. CHAN - Folsom CA, US
Assignee:
Soft Machines, Inc. - Santa Clara CA
International Classification:
G06F 9/48
US Classification:
718103, 718102
Abstract:
A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor is disclosed. The method comprises selecting and dispatching a plurality of instructions from a plurality of select ports in a scheduler module in first clock cycle. Next, it comprises determining if a first physical register file unit has capacity to support instructions dispatched in the first clock cycle. Further, it comprises supplying a response back to logic circuitry between the plurality of select ports and a plurality of execution ports, wherein the logic circuitry is operable to re-map select ports in the scheduler module to execution ports based on the response. Finally, responsive to a determination that the first physical register file unit is full, the method comprises re-mapping at least one select port connecting with an execution unit in the first physical register file unit to a second physical register file unit.

Possible Relatives

David Chan  Dawn A Chan  Dean A Chan  Daniel K Chan  Aaron H Chan  Danielle M Chan  Dennis Y Chan  Nelson C Johnson  Nelson C Stanley  Nelson L Steele 

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