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Nicholas R Watts, Age 63508 Brookwood Ct, Phoenix, AZ 85048

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Known as:
Nicholas Randolph Watts Nick R Watts

Nicholas Watts Phones & Addresses

508 Brookwood Ct, Phoenix, AZ 85048 (480) 460-3270

Portland, OR

Beaverton, OR

Happy Valley, OR

Cincinnati, OH

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Nicholas Watts Photo 44

Nicholas R Watts

Location:
Phoenix, AZ
Industry:
Semiconductors
Skills:
Semiconductors, Ic, Design of Experiments, Failure Analysis, Soc, Semiconductor Industry, Spc, Jmp, Manufacturing, Product Engineering, R&D, Simulations, Cross Functional Team Leadership, Engineering Management
Nicholas Watts Photo 45

Lamar Consolidated High School

Work:

Lamar Consolidated High School
Nicholas Watts Photo 46

Nicholas Watts

Publications & IP owners

Us Patents

Electronic Circuit Housing With Trench Vias And Method Of Fabrication Therefor

US Patent:
6556453, Apr 29, 2003
Filed:
Dec 13, 2000
Appl. No.:
09/735956
Inventors:
David G. Figueroa - Mesa AZ
Nicholas R. Watts - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 118
US Classification:
361763, 361760, 361761, 361762, 361764, 361766, 361811, 174260, 174261
Abstract:
An electronic circuit package ( , FIG. ) includes one or more trench vias ( , FIG. ). Each trench via makes electrical contact with one or more terminals ( , FIG. ) of a discrete device ( , FIG. ) embedded within the package. A trench via can extend to a surface of the package, or one or more conventional vias ( , FIG. ) formed within layers ( , FIG. ) above or below the trench via can electrically connect the trench via, and thus the discrete device, to the surface of the package. The discrete device ( , FIG. ) can be a capacitor, in one embodiment, providing decoupling capacitance to an integrated circuit load. Besides being implemented in a package, the trench vias also could be implemented in other types of electronic circuit housings (e. g. , interposers, sockets, and printed circuit boards).

Multilayer Capacitor, Wiring Board, Decoupling Circuit, And High Frequency Circuit Incorporating The Same

US Patent:
6606237, Aug 12, 2003
Filed:
Jun 27, 2002
Appl. No.:
10/180629
Inventors:
Yasuyuki Naito - Otsu, JP
Masaaki Taniguchi - Fukui-ken, JP
Yoichi Kuroda - Fukui, JP
Haruo Hori - Sabae, JP
David G. Figueroa - Mesa AZ
Jorge P. Rodriguez - Portland OR
Nicholas R. Watts - Phoenix AZ
Nicholas L. Holmberg - Gilbert AZ
Takashi Hioki - Tsukuba, JP
Assignee:
Murata Manufacturing Co., Ltd. - Kyoto
Intel Corporation - Santa Clara CA
International Classification:
H01G 4228
US Classification:
3613063, 361361, 361303, 3613062
Abstract:
A multilayer capacitor is constructed to minimize equivalent series inductance (ESL) and to achieve large capacitance. The capacitor includes first and second main go surface terminal electrodes provided on a first main surface of the main body of the multilayer capacitor. First and second side surface terminal electrodes are disposed on four side surfaces of the main body. The main body is divided into a low ESL section of the first main-surface side and a high capacitance section of the second main-surface side. In the low ESL section, in addition to first and second low ESL internal electrodes, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode are provided. In the high capacitance section, in addition to first and second high capacitance internal electrodes, a first leading electrode electrically connecting the first high capacitance internal electrode to the first side surface terminal electrode and a second leading electrode electrically connecting the second high capacitance internal electrode to the second side surface terminal electrode are provided.

Via Including Multiple Electrical Paths

US Patent:
7183653, Feb 27, 2007
Filed:
Dec 17, 2003
Appl. No.:
10/740957
Inventors:
Todd B Myers - Chandler AZ, US
Nicholas R. Watts - Phoenix AZ, US
Eric C Palmer - Tempe AZ, US
Renee M Defeo - Chandler AZ, US
Jui Min Lim - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
H01L 23/52
Z01L 29/40
US Classification:
257774, 257758, 257698
Abstract:
A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Method Of Embedding Passive Component Within Via

US Patent:
7275316, Oct 2, 2007
Filed:
Mar 31, 2004
Appl. No.:
10/815464
Inventors:
Todd B Myers - Gilbert AZ, US
Nicholas R. Watts - Phoenix AZ, US
Eric C Palmer - Tempe AZ, US
Jui Min Lim - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01K 3/10
US Classification:
29852, 29 2542, 295921, 29832, 29833, 29834, 29842, 174 524, 174261, 174262, 257774, 257916, 257E23067, 3613213, 361760
Abstract:
A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Via Including Multiple Electrical Paths

US Patent:
7737025, Jun 15, 2010
Filed:
Jan 24, 2007
Appl. No.:
11/626606
Inventors:
Todd B Myers - Gilbert AZ, US
Nicholas R. Watts - Phoenix AZ, US
Eric C Palmer - Tempe AZ, US
Renee M Defeo - Chandler AZ, US
Jui Min Lim - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438637, 438396, 438106, 438612, 438629, 438668, 438638, 438639, 438640, 257750, 257774, 257E23067
Abstract:
A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Method Of Stiffening Coreless Package Substrate

US Patent:
7851269, Dec 14, 2010
Filed:
Feb 19, 2009
Appl. No.:
12/378953
Inventors:
Sriram Muthukumar - Chandler AZ, US
Nicholas R. Watts - Phoenix AZ, US
John S. Guzek - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438125, 438121, 438122
Abstract:
Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

Semiconductor Device With Package To Package Connection

US Patent:
7952182, May 31, 2011
Filed:
Jun 30, 2008
Appl. No.:
12/165315
Inventors:
Nicholas Randolph Watts - Phoenix AZ, US
Javier Soto Gonzalez - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
257686, 438121, 257E23001
Abstract:
A semiconductor package comprises a first package; a second package that is provided on the first package; and a first interconnect that comprises a bump to couple to the first package and a base material layer to cover the bump, wherein the second package is supported on the base material layer that is coupled to the bump.

Method Of Embedding Passive Component Within Via

US Patent:
7952202, May 31, 2011
Filed:
Aug 30, 2007
Appl. No.:
11/847985
Inventors:
Todd B Myers - Gilbert AZ, US
Nicholas R. Watts - Phoenix AZ, US
Eric C Palmer - Tempe AZ, US
Jui Min Lim - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
H01L 23/52
US Classification:
257774, 257773
Abstract:
A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Isbn (Books And Publications)

Environmental Policy And Politics

Author:
Nicholas Watts
ISBN #:
0063182807

Possible Relatives

David A Watts  Deana M Watts  Dale B Watts  Damien J Watts  Damon L Watts  Dana K Watts  Daniel P Watts  Nicholas V Johnson  Nicholas J Stanko  Nicholas G Stanton 

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